Doug Joseph

Person

Danbury, CT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pre-fetching address translation for computation offloading
- Patent number 12,353,333
- Issue date Jul 8, 2025
- Samsung Electronics Co., Ltd.
- Aditya Madhusudan Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimensional routing architecture
- Patent number 12,316,537
- Issue date May 27, 2025
- ARM Limited
- Alejandro Rico Carro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory architecture
- Patent number 11,954,040
- Issue date Apr 9, 2024
- ARM Limited
- Alejandro Rico Carro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power aware scheduling of requests in 3D chip stack
- Patent number 11,169,848
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Philip Jacob
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional chip-based regular expression scanner
- Patent number 10,740,116
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Jan Van Lunteren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power aware scheduling of requests in 3D chip stack
- Patent number 10,579,425
- Issue date Mar 3, 2020
- International Business Machines Corporation
- Philip Jacob
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient calibration of a low power parallel data communications c...
- Patent number 9,684,629
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Timothy O. Dickson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient calibration of a low power parallel data communications c...
- Patent number 9,411,750
- Issue date Aug 9, 2016
- International Business Machines Corporation
- Timothy O. Dickson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory system connector
- Patent number 9,298,395
- Issue date Mar 29, 2016
- GLOBALFOUNDRIES Inc.
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device refresh
- Patent number 9,053,811
- Issue date Jun 9, 2015
- International Business Machines Corporation
- Paul W. Coteus
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel receiver interface with receiver redundancy
- Patent number 9,001,842
- Issue date Apr 7, 2015
- International Business Machines Corporation
- Timothy O. Dickson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Soft error protection in individual memory devices
- Patent number 8,949,685
- Issue date Feb 3, 2015
- International Business Machines Corporation
- Douglas J. Joseph
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for multithreaded text indexing for next generati...
- Patent number 8,661,037
- Issue date Feb 25, 2014
- International Business Machines Corporation
- Ankur Narang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of hardware to manage dependencies between groups of network da...
- Patent number 8,311,051
- Issue date Nov 13, 2012
- International Business Machines Corporation
- Douglas G. Balazich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for massively parallel multi-core text indexing
- Patent number 8,229,916
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Ankur Narang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection in multi-chip with interposers and bridges
- Patent number 8,138,015
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Douglas James Joseph
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridges for interconnecting interposers in multi-chip integrated ci...
- Patent number 8,008,764
- Issue date Aug 30, 2011
- International Business Machines Corporation
- Douglas James Joseph
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Receive queue device with efficient queue flow control, segment pla...
- Patent number 7,912,988
- Issue date Mar 22, 2011
- International Business Machines Corporation
- William Todd Boyd
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Split socket send queue apparatus and method with efficient queue f...
- Patent number 7,818,362
- Issue date Oct 19, 2010
- International Business Machines Corporation
- William Todd Boyd
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Use of hardware to manage dependencies between groups of network da...
- Patent number 7,724,757
- Issue date May 25, 2010
- International Business Machines Corporation
- Douglas G. Balazich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft error protection in individual memory devices
- Patent number 7,721,182
- Issue date May 18, 2010
- International Business Machines Corporation
- Douglas J. Joseph
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split socket send queue apparatus and method with efficient queue f...
- Patent number 7,519,650
- Issue date Apr 14, 2009
- International Business Machines Corporation
- William Todd Boyd
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Use of hardware to manage dependencies between groups of network da...
- Patent number 7,408,945
- Issue date Aug 5, 2008
- International Business Machines Corporation
- Douglas G. Balazich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method using hardware buffers for processing microcode t...
- Patent number 7,353,429
- Issue date Apr 1, 2008
- International Business Machines Corporation
- Walker B. Carroll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management offload for RDMA enabled network adapters
- Patent number 7,299,266
- Issue date Nov 20, 2007
- International Business Machines Corporation
- William Todd Boyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure inter-node communication
- Patent number 7,231,519
- Issue date Jun 12, 2007
- International Business Machines Corporation
- Doug Joseph
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Read-modify-write avoidance using a boundary word storage mechanism
- Patent number 7,099,997
- Issue date Aug 29, 2006
- International Business Machines Corporation
- Douglas G. Balazich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lazy deregistration protocol for a split socket stack
- Patent number 6,823,437
- Issue date Nov 23, 2004
- International Business Machines Corporation
- William Todd Boyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data reordering mechanism for high performance networks
- Patent number 6,735,647
- Issue date May 11, 2004
- International Business Machines Corporation
- William Todd Boyd
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Remote direct memory access enabled network interface controller sw...
- Patent number 6,721,806
- Issue date Apr 13, 2004
- International Business Machines Corporation
- William Todd Boyd
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD OF HANDLING MODIFICATION TRACKING DATA IN TIMESTE...
- Publication number 20250190377
- Publication date Jun 12, 2025
- Samsung Electronics Co., Ltd.
- Thomas Labonte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES
- Publication number 20250139010
- Publication date May 1, 2025
- Samsung Electronics Co., Ltd.
- Alan GARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES
- Publication number 20250139007
- Publication date May 1, 2025
- Samsung Electronics Co., Ltd.
- Alan GARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR A CACHE DIRECTORY FOR A MULTI-L...
- Publication number 20250139006
- Publication date May 1, 2025
- Samsung Electronics Co., Ltd.
- Aditya Madhusudan DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES
- Publication number 20250139012
- Publication date May 1, 2025
- Samsung Electronics Co., Ltd.
- Alan GARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-FETCHING ADDRESS TRANSLATION FOR COMPUTATION OFFLOADING
- Publication number 20250117337
- Publication date Apr 10, 2025
- Samsung Electronics Co., Ltd.
- Aditya Madhusudan DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA STRUCTURE MARSHALLING UNIT
- Publication number 20250077499
- Publication date Mar 6, 2025
- ARM Limited
- Marco SIRACUSA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR RANDOM NUMBER GENERATOR SEED CREATION USING UNINITIALIZE...
- Publication number 20240348434
- Publication date Oct 17, 2024
- Samsung Electronics Co., Ltd.
- Andrew Thomas TAUFERNER
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEMS AND METHODS FOR DISTRIBUTING WORK BETWEEN A HOST AND AN ACC...
- Publication number 20240330188
- Publication date Oct 3, 2024
- Samsung Electronics Co., Ltd.
- Jai Dayal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS TRANSLATION IN A MULTI-NODE COMPUTING SYSTEM
- Publication number 20240330201
- Publication date Oct 3, 2024
- Samsung Electronics Co., Ltd.
- Alan Gara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERY LARGE ADDRESS SPACE USING EXTENDED PAGE TABLES
- Publication number 20240311289
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- David Lombard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PACKAGE EXPANSION
- Publication number 20240315055
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- Casey Glenn THIELEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES
- Publication number 20240311308
- Publication date Sep 19, 2024
- Samsung Electronics Co., LTD
- Arun Francis RODRIGUES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES
- Publication number 20240311315
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- Alan GARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR REMOTE MEMORY ACCESS BY NODES
- Publication number 20240311316
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- David LOMBARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Dimensional Routing Architecture
- Publication number 20230037714
- Publication date Feb 9, 2023
- ARM Limited
- Alejandro Rico Carro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Memory Architecture
- Publication number 20210390059
- Publication date Dec 16, 2021
- ARM Limited
- Alejandro Rico Carro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER AWARE SCHEDULING OF REQUESTS IN 3D CHIP STACK
- Publication number 20200285512
- Publication date Sep 10, 2020
- International Business Machines Corporation
- Philip Jacob
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL CHIP-BASED REGULAR EXPRESSION SCANNER
- Publication number 20170061304
- Publication date Mar 2, 2017
- International Business Machines Corporation
- Jan Van Lunteren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Calibration of a Low Power Parallel Data Communications C...
- Publication number 20160239459
- Publication date Aug 18, 2016
- International Business Machines Corporation
- Timothy O. Dickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM CONNECTOR
- Publication number 20140115281
- Publication date Apr 24, 2014
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE REFRESH
- Publication number 20140071778
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Calibration of a Low Power Parallel Data Communications C...
- Publication number 20140032799
- Publication date Jan 30, 2014
- International Business Machines Corporation
- Timothy O. Dickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL RECEIVER INTERFACE WITH RECEIVER REDUNDANCY
- Publication number 20130343401
- Publication date Dec 26, 2013
- International Business Machines Corporation
- Timothy O. Dickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTION IN MULTI-CHIP WITH INTERPOSERS AND BRIDGES
- Publication number 20110312129
- Publication date Dec 22, 2011
- International Business Machines Corporation
- Douglas James Joseph
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR MULTITHREADED TEXT INDEXING FOR NEXT GENERATI...
- Publication number 20110252033
- Publication date Oct 13, 2011
- International Business Machines Corporation
- ANKUR NARANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF HARDWARE TO MANAGE DEPENDENCIES BETWEEN GROUPS OF NETWORK DA...
- Publication number 20100179989
- Publication date Jul 15, 2010
- International Business Machines Corporation
- Douglas G. Balazich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Soft Error Protection in Individual Memory Devices
- Publication number 20100146369
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Douglas J. Joseph
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MASSIVELY PARALLEL MULTI-CORE TEXT INDEXING
- Publication number 20100094870
- Publication date Apr 15, 2010
- Ankur Narang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRIDGES FOR INTERCONNECTING INTERPOSERS IN MULTI-CHIP INTEGRATED CI...
- Publication number 20090267238
- Publication date Oct 29, 2009
- Douglas James Joseph
- H01 - BASIC ELECTRIC ELEMENTS

Doug Joseph

Person

Patents Grantslast 30 patents

Pre-fetching address translation for computation offloading

Multi-dimensional routing architecture

Cache memory architecture

Power aware scheduling of requests in 3D chip stack

Three-dimensional chip-based regular expression scanner

Power aware scheduling of requests in 3D chip stack

Efficient calibration of a low power parallel data communications c...

Efficient calibration of a low power parallel data communications c...

Memory system connector

Memory device refresh

Parallel receiver interface with receiver redundancy

Soft error protection in individual memory devices

System and method for multithreaded text indexing for next generati...

Use of hardware to manage dependencies between groups of network da...

Method for massively parallel multi-core text indexing

Interconnection in multi-chip with interposers and bridges

Bridges for interconnecting interposers in multi-chip integrated ci...

Receive queue device with efficient queue flow control, segment pla...

Split socket send queue apparatus and method with efficient queue f...

Use of hardware to manage dependencies between groups of network da...

Soft error protection in individual memory devices

Split socket send queue apparatus and method with efficient queue f...

Use of hardware to manage dependencies between groups of network da...

System and method using hardware buffers for processing microcode t...

Memory management offload for RDMA enabled network adapters

Secure inter-node communication

Read-modify-write avoidance using a boundary word storage mechanism

Lazy deregistration protocol for a split socket stack

Data reordering mechanism for high performance networks

Remote direct memory access enabled network interface controller sw...

Patents Applicationslast 30 patents

SYSTEM AND METHOD OF HANDLING MODIFICATION TRACKING DATA IN TIMESTE...

SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES

SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES

SYSTEMS, METHODS, AND APPARATUS FOR A CACHE DIRECTORY FOR A MULTI-L...

SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES

PRE-FETCHING ADDRESS TRANSLATION FOR COMPUTATION OFFLOADING

DATA STRUCTURE MARSHALLING UNIT

METHOD FOR RANDOM NUMBER GENERATOR SEED CREATION USING UNINITIALIZE...

SYSTEMS AND METHODS FOR DISTRIBUTING WORK BETWEEN A HOST AND AN ACC...

ADDRESS TRANSLATION IN A MULTI-NODE COMPUTING SYSTEM

VERY LARGE ADDRESS SPACE USING EXTENDED PAGE TABLES

MEMORY PACKAGE EXPANSION

SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES

SYSTEMS AND METHODS FOR COMPUTING WITH MULTIPLE NODES

SYSTEMS, METHODS, AND APPARATUS FOR REMOTE MEMORY ACCESS BY NODES

Multi-Dimensional Routing Architecture

Cache Memory Architecture

POWER AWARE SCHEDULING OF REQUESTS IN 3D CHIP STACK

THREE-DIMENSIONAL CHIP-BASED REGULAR EXPRESSION SCANNER

Efficient Calibration of a Low Power Parallel Data Communications C...

MEMORY SYSTEM CONNECTOR

MEMORY DEVICE REFRESH

Efficient Calibration of a Low Power Parallel Data Communications C...

PARALLEL RECEIVER INTERFACE WITH RECEIVER REDUNDANCY

INTERCONNECTION IN MULTI-CHIP WITH INTERPOSERS AND BRIDGES

SYSTEM AND METHOD FOR MULTITHREADED TEXT INDEXING FOR NEXT GENERATI...

USE OF HARDWARE TO MANAGE DEPENDENCIES BETWEEN GROUPS OF NETWORK DA...

Soft Error Protection in Individual Memory Devices

METHOD FOR MASSIVELY PARALLEL MULTI-CORE TEXT INDEXING

BRIDGES FOR INTERCONNECTING INTERPOSERS IN MULTI-CHIP INTEGRATED CI...