Doug Meyer

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for high-speed data bus connection and fabric...
- Patent number 11,593,291
- Issue date Feb 28, 2023
- GigaIO Networks, Inc.
- Eric Pilmore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for DMA engine descriptors for high speed dat...
- Patent number 11,392,528
- Issue date Jul 19, 2022
- CIGAIO NETWORKS, INC.
- Doug Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed contiguous reads in a network on a chip architecture
- Patent number 10,346,049
- Issue date Jul 9, 2019
- FRIDAY HARBOR LLC
- Andrew White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Writing to contiguous memory addresses in a network on a chip archi...
- Patent number 10,152,352
- Issue date Dec 11, 2018
- FRIDAY HARBOR LLC
- Andy White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chained packet sequences in a network on a chip architecture
- Patent number 10,027,583
- Issue date Jul 17, 2018
- KnuEdge Incorporated
- Andrew White
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronization in a multi-processor computing system
- Patent number 9,910,716
- Issue date Mar 6, 2018
- KnuEdge Incorporated
- Douglas B. Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing write operations in a network on a chip device
- Patent number 9,864,519
- Issue date Jan 9, 2018
- KnuEdge Incorporated
- Doug Meyer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Performing read operations in network on a chip architecture
- Patent number 9,686,191
- Issue date Jun 20, 2017
- KnuEdge Incorporation
- Andy White
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Topology discovery in a computing system
- Patent number 9,634,901
- Issue date Apr 25, 2017
- KnuEdge Incorporated
- Douglas A. Palmer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic self-tuning soft-error-rate-discrimination for enhanced ava...
- Patent number 7,526,683
- Issue date Apr 28, 2009
- Sun Microsystems, Inc.
- Lawrence G. Votta, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for expressing the algorithms for the manipulatio...
- Patent number 7,367,016
- Issue date Apr 29, 2008
- Sun Microsystems, Inc.
- Douglas B. Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnostic cage for testing redundant system controllers
- Patent number 6,760,868
- Issue date Jul 6, 2004
- Sun Microsystems, Inc.
- Daniel P. Drogichen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cage for dynamic attach testing of I/O boards
- Patent number 6,571,360
- Issue date May 27, 2003
- Sun Microsystems, Inc.
- Daniel P. Drogichen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnostic cage for testing redundant system controllers
- Patent number 6,425,094
- Issue date Jul 23, 2002
- Sun Microsystems, Inc.
- Daniel P. Drogichen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transparent relocation of real memory addresses in the main memory...
- Patent number 5,765,198
- Issue date Jun 9, 1998
- Cray Research, Inc.
- Andrew Jackson McCrocklin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR DATA DESCRIPTORS FOR HIGH SPEED DATA SYSTEMS
- Publication number 20220283975
- Publication date Sep 8, 2022
- GigaIO Networks, Inc.
- Doug Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR DMA ENGINE DESCRIPTORS FOR HIGH SPEED DAT...
- Publication number 20210124706
- Publication date Apr 29, 2021
- GigaIO Networks, Inc.
- Doug Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR HIGH-SPEED DATA BUS CONNECTION AND FABRIC...
- Publication number 20200081858
- Publication date Mar 12, 2020
- GigaIO Networks, Inc.
- Eric Philmore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network Processor Inter-Device Packet Source ID Tagging for Domain...
- Publication number 20180048562
- Publication date Feb 15, 2018
- KnuEdge Incorporated
- Douglas B. Meyer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Application Domain Security
- Publication number 20180006938
- Publication date Jan 4, 2018
- KnuEdge Incorporated
- Douglas B. Meyer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Distributed Contiguous Reads in a Network on a Chip Architecture
- Publication number 20170315726
- Publication date Nov 2, 2017
- KnuEdge Incorporated
- Andrew White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chained Packet Sequences in a Network on a Chip Architecture
- Publication number 20170279714
- Publication date Sep 28, 2017
- KnuEdge Incorporated
- Andrew White
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronization in a Multi-Processor Computing System
- Publication number 20170262318
- Publication date Sep 14, 2017
- KnuEdge Incorporated
- Douglas B. Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING AN OPERATION STATE WITHIN A COMPUTING SYSTEM WITH MULTI...
- Publication number 20170220520
- Publication date Aug 3, 2017
- KnuEdge Incorporated
- Douglas Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Writing to Contiguous Memory Addresses in a Network on a Chip Archi...
- Publication number 20170139644
- Publication date May 18, 2017
- Intellisis Corporation
- Andy White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Write Operations In A Network On A Chip Device
- Publication number 20170060420
- Publication date Mar 2, 2017
- KnuEdge Incorporated
- Doug Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Read Operations in Network on a Chip Architecture
- Publication number 20170054635
- Publication date Feb 23, 2017
- Knu Edge Incorporated
- Andy White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synchronization in a Computing System with Multi-Core Processing De...
- Publication number 20160224502
- Publication date Aug 4, 2016
- The Intellisis Corporation
- Douglas A. PALMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Topology Discovery in a Computing System
- Publication number 20160226712
- Publication date Aug 4, 2016
- The Intellisis Corporation
- Douglas A. PALMER
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronization in a Multi-Processor Computing System
- Publication number 20160224398
- Publication date Aug 4, 2016
- Intellisis Corporation
- Douglas A. Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for expressing the algorithms for the manipulatio...
- Publication number 20050015778
- Publication date Jan 20, 2005
- Sun Microsystems, Inc.
- Douglas B. Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Diagnostic cage for testing redundant system controllers
- Publication number 20020152421
- Publication date Oct 17, 2002
- Sun Microsystems, Inc.
- Daniel P. Drogichen
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Methods and apparatus for high-speed data bus connection and fabric...

Methods and apparatus for DMA engine descriptors for high speed dat...

Distributed contiguous reads in a network on a chip architecture

Writing to contiguous memory addresses in a network on a chip archi...

Chained packet sequences in a network on a chip architecture

Synchronization in a multi-processor computing system

Performing write operations in a network on a chip device

Performing read operations in network on a chip architecture

Topology discovery in a computing system

Dynamic self-tuning soft-error-rate-discrimination for enhanced ava...

Method and system for expressing the algorithms for the manipulatio...

Diagnostic cage for testing redundant system controllers

Cage for dynamic attach testing of I/O boards

Diagnostic cage for testing redundant system controllers

Transparent relocation of real memory addresses in the main memory...

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR DATA DESCRIPTORS FOR HIGH SPEED DATA SYSTEMS

METHODS AND APPARATUS FOR DMA ENGINE DESCRIPTORS FOR HIGH SPEED DAT...

METHODS AND APPARATUS FOR HIGH-SPEED DATA BUS CONNECTION AND FABRIC...

Network Processor Inter-Device Packet Source ID Tagging for Domain...

Application Domain Security

Distributed Contiguous Reads in a Network on a Chip Architecture

Chained Packet Sequences in a Network on a Chip Architecture

Synchronization in a Multi-Processor Computing System

DETERMINING AN OPERATION STATE WITHIN A COMPUTING SYSTEM WITH MULTI...

Writing to Contiguous Memory Addresses in a Network on a Chip Archi...

Performing Write Operations In A Network On A Chip Device

Performing Read Operations in Network on a Chip Architecture

Synchronization in a Computing System with Multi-Core Processing De...

Topology Discovery in a Computing System

Synchronization in a Multi-Processor Computing System

Method and system for expressing the algorithms for the manipulatio...

Diagnostic cage for testing redundant system controllers