Douglas F. Pastorello

Person

Hudson, NH, US

People

Patents Grantslast 30 patents

Information Patent Grant
Calibration of a time-to-digital converter using a virtual phase-lo...
- Patent number 11,888,493
- Issue date Jan 30, 2024
- Skyworks Solutions, Inc.
- Timothy Adam Monk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Calibration of a time-to-digital converter using a virtual phase-lo...
- Patent number 11,563,441
- Issue date Jan 24, 2023
- Skyworks Solutions, Inc.
- Timothy Adam Monk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Calibration of a time-to-digital converter using a virtual phase-lo...
- Patent number 11,283,459
- Issue date Mar 22, 2022
- Skyworks Solutions, Inc.
- Timothy Adam Monk
- G04 - HOROLOGY
Information Patent Grant
Calibration of an interpolative divider using a virtual phase-locke...
- Patent number 10,833,682
- Issue date Nov 10, 2020
- Silicon Laboratories Inc.
- Timothy A. Monk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spur cancellation in a PLL system with an automatically updated tar...
- Patent number 10,819,353
- Issue date Oct 27, 2020
- Silicon Laboratories Inc.
- Timothy A. Monk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Metastable-free output synchronization for multiple-chip systems an...
- Patent number 10,511,312
- Issue date Dec 17, 2019
- Silicon Laboratories Inc.
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential voltage-controlled oscillator analog-to-digital conver...
- Patent number 9,588,497
- Issue date Mar 7, 2017
- Silicon Laboratories Inc.
- Timothy A. Monk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable I/O cell capable of holding its state in power-down mode
- Patent number 8,041,975
- Issue date Oct 18, 2011
- Silicon Laboratories Inc.
- Biranchinath Sahu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory power controller
- Patent number 8,020,010
- Issue date Sep 13, 2011
- Silicon Laboratories Inc.
- Douglas F. Pastorello
- G11 - INFORMATION STORAGE
Information Patent Grant
Microcontroller unit (MCU) with power saving mode
- Patent number 8,010,819
- Issue date Aug 30, 2011
- Silicon Laboratories
- Douglas F. Pastorello
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tri-level test mode terminal in limited terminal environment
- Patent number 7,562,275
- Issue date Jul 14, 2009
- Silicon Laboratories Inc.
- Richard Juhn
- G01 - MEASURING TESTING
Information Patent Grant
High-speed divider with reduced power consumption
- Patent number 7,551,009
- Issue date Jun 23, 2009
- Silicon Laboratories Inc.
- Akhil K. Garlapati
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency detector including a variable delay filter
- Patent number 7,502,434
- Issue date Mar 10, 2009
- Silicon Laboratories Inc.
- Eric T. King
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
MCU with power saving mode
- Patent number 7,441,131
- Issue date Oct 21, 2008
- Silicon Laboratories Inc.
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed divider with pulse-width control
- Patent number 7,405,601
- Issue date Jul 29, 2008
- Silicon Laboratories Inc.
- Akhil K. Garlapati
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable I/O cell capable of holding its state in power-down mode
- Patent number 7,373,533
- Issue date May 13, 2008
- Silicon Laboratories
- Biranchinath Sahu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase selectable divider circuit
- Patent number 7,187,216
- Issue date Mar 6, 2007
- Silicon Laboratories Inc.
- Lizhong Sun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable frequency divider
- Patent number 7,113,009
- Issue date Sep 26, 2006
- Silicon Laboratories Inc.
- Lizhong Sun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Auto-detection between referenceless and reference clock mode of op...
- Patent number 6,831,523
- Issue date Dec 14, 2004
- Silicon Laboratories Inc.
- Douglas F. Pastorello
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for handling a framing error at a serial inter...
- Patent number 6,760,854
- Issue date Jul 6, 2004
- Cirrus Logic, Inc.
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Offset correction and slicing level adjustment for amplifier circuits
- Patent number 6,657,488
- Issue date Dec 2, 2003
- Silicon Laboratories, Inc.
- Eric T. King
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Throughput for a serial interface
- Patent number 6,557,051
- Issue date Apr 29, 2003
- Cirrus Logic, Inc.
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay systems and methods using a variable delay SINC filter
- Patent number 6,531,906
- Issue date Mar 11, 2003
- Cirrus Logic, Inc.
- William F. Gardei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Energy-to-pulse converter systems, devices, and methods wherein the...
- Patent number 6,522,982
- Issue date Feb 18, 2003
- Cirrus Logic, Inc.
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single wire interface for an analog to digital converter
- Patent number 6,487,674
- Issue date Nov 26, 2002
- Cirrus Logic, Inc.
- Joe White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single phase bi-directional electrical measurement systems and meth...
- Patent number 6,417,792
- Issue date Jul 9, 2002
- Cirrus Logic, Inc.
- Eric T. King
- G01 - MEASURING TESTING
Information Patent Grant
Definition of physical level of a logic output by a logic input
- Patent number 6,377,198
- Issue date Apr 23, 2002
- Cirrus Logic Inc.
- Jerome Johnston
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase compensation methods and systems for a dual-channel a...
- Patent number 6,373,415
- Issue date Apr 16, 2002
- Cirrus Logic, Inc.
- Eric T. King
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay systems and methods using a variable delay sinc filter
- Patent number 6,369,634
- Issue date Apr 9, 2002
- Cirrus Logic, Inc.
- William F. Gardei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay correction system and method for a voltage channel in a sampl...
- Patent number 6,304,202
- Issue date Oct 16, 2001
- Cirrus Logic, Inc.
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CALIBRATION OF A TIME-TO-DIGITAL CONVERTER USING A VIRTUAL PHASE-LO...
- Publication number 20230231567
- Publication date Jul 20, 2023
- Skyworks Solutions, Inc.
- Timothy Adam Monk
- G04 - HOROLOGY
Information Patent Application
CALIBRATION OF A TIME-TO-DIGITAL CONVERTER USING A VIRTUAL PHASE-LO...
- Publication number 20220321137
- Publication date Oct 6, 2022
- Skyworks Solutions, Inc.
- Timothy Adam Monk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MODIFIED FIRST-ORDER NOISE-SHAPING DYNAMIC-ELEMENT-MATCHING TECHNIQUE
- Publication number 20140118172
- Publication date May 1, 2014
- Silicon Laboratories Inc.
- Xue-Mei Gong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY POWER CONTROLLER
- Publication number 20090319814
- Publication date Dec 24, 2009
- Silicon Laboratories Inc.
- DOUGLAS F. PASTORELLO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MCU WITH POWER SAVING MODE
- Publication number 20090187773
- Publication date Jul 23, 2009
- Silicon Laboratories Inc.
- DOUGLAS F. PASTORELLO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE I/O CELL CAPABLE OF HOLDING ITS STATE IN POWER-DOWN MODE
- Publication number 20080246526
- Publication date Oct 9, 2008
- Silicon Laboratories Inc.
- BIRANCHINATH SAHU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH-SPEED DIVIDER WITH REDUCED POWER CONSUMPTION
- Publication number 20080204088
- Publication date Aug 28, 2008
- Akhil K. Garlapati
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRI-LEVEL TEST MODE TERMINAL IN LIMITED TERMINAL ENVIRONMENT
- Publication number 20080091992
- Publication date Apr 17, 2008
- Richard Juhn
- G01 - MEASURING TESTING
Information Patent Application
HIGH-SPEED DIVIDER WITH PULSE-WIDTH CONTROL
- Publication number 20070139088
- Publication date Jun 21, 2007
- Akhil K. Garlapati
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MCU with power saving mode
- Publication number 20070079148
- Publication date Apr 5, 2007
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable I/O cell capable of holding its state in power-down mode
- Publication number 20070079149
- Publication date Apr 5, 2007
- Biranchinath Sahu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase selectable divider circuit
- Publication number 20050242848
- Publication date Nov 3, 2005
- Silicon Laboratories Inc.
- Lizhong Sun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Frequency detector including a variable delay filter
- Publication number 20050220233
- Publication date Oct 6, 2005
- Silicon Laboratories, Inc.
- Eric T. King
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable frequency divider
- Publication number 20050212570
- Publication date Sep 29, 2005
- Silicon Laboratories, Inc.
- Lizhong Sun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Prompt resynchronization for a serial interface
- Publication number 20030196130
- Publication date Oct 16, 2003
- Cirrus Logic, Inc.
- Douglas F. Pastorello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Version with markings to show changes made
- Publication number 20020039041
- Publication date Apr 4, 2002
- William F. Gardei
- H03 - BASIC ELECTRONIC CIRCUITRY

Douglas F. Pastorello

Person

Patents Grantslast 30 patents

Calibration of a time-to-digital converter using a virtual phase-lo...

Calibration of a time-to-digital converter using a virtual phase-lo...

Calibration of a time-to-digital converter using a virtual phase-lo...

Calibration of an interpolative divider using a virtual phase-locke...

Spur cancellation in a PLL system with an automatically updated tar...

Metastable-free output synchronization for multiple-chip systems an...

Differential voltage-controlled oscillator analog-to-digital conver...

Programmable I/O cell capable of holding its state in power-down mode

Memory power controller

Microcontroller unit (MCU) with power saving mode

Tri-level test mode terminal in limited terminal environment

High-speed divider with reduced power consumption

Frequency detector including a variable delay filter

MCU with power saving mode

High-speed divider with pulse-width control

Programmable I/O cell capable of holding its state in power-down mode

Phase selectable divider circuit

Programmable frequency divider

Auto-detection between referenceless and reference clock mode of op...

Method and apparatus for handling a framing error at a serial inter...

Offset correction and slicing level adjustment for amplifier circuits

Throughput for a serial interface

Delay systems and methods using a variable delay SINC filter

Energy-to-pulse converter systems, devices, and methods wherein the...

Single wire interface for an analog to digital converter

Single phase bi-directional electrical measurement systems and meth...

Definition of physical level of a logic output by a logic input

Digital phase compensation methods and systems for a dual-channel a...

Delay systems and methods using a variable delay sinc filter

Delay correction system and method for a voltage channel in a sampl...

Patents Applicationslast 30 patents

CALIBRATION OF A TIME-TO-DIGITAL CONVERTER USING A VIRTUAL PHASE-LO...

CALIBRATION OF A TIME-TO-DIGITAL CONVERTER USING A VIRTUAL PHASE-LO...

MODIFIED FIRST-ORDER NOISE-SHAPING DYNAMIC-ELEMENT-MATCHING TECHNIQUE

MEMORY POWER CONTROLLER

MCU WITH POWER SAVING MODE

PROGRAMMABLE I/O CELL CAPABLE OF HOLDING ITS STATE IN POWER-DOWN MODE

HIGH-SPEED DIVIDER WITH REDUCED POWER CONSUMPTION

TRI-LEVEL TEST MODE TERMINAL IN LIMITED TERMINAL ENVIRONMENT

HIGH-SPEED DIVIDER WITH PULSE-WIDTH CONTROL

MCU with power saving mode

Programmable I/O cell capable of holding its state in power-down mode

Phase selectable divider circuit

Frequency detector including a variable delay filter

Programmable frequency divider

Prompt resynchronization for a serial interface

Version with markings to show changes made