Douglas M. TRICKETT

Person

Altamont, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chamferless via structures
- Patent number 10,957,588
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Mark L. Lenhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless via structures
- Patent number 10,937,694
- Issue date Mar 2, 2021
- International Business Machines Corporation
- Mark L. Lenhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless via structures
- Patent number 10,903,118
- Issue date Jan 26, 2021
- International Business Machines Corporation
- Mark L. Lenhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless via structures
- Patent number 10,388,565
- Issue date Aug 20, 2019
- International Business Machines Corporation
- Mark L. Lenhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless via structures
- Patent number 10,032,668
- Issue date Jul 24, 2018
- International Business Machines Corporation
- Mark L. Lenhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned via in integrated circuit
- Patent number 9,768,113
- Issue date Sep 19, 2017
- International Business Machines Corporation
- Yannick Feurprier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless via structures
- Patent number 9,613,862
- Issue date Apr 4, 2017
- International Business Machines Corporation
- Mark L. Lenhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned via in integrated circuit
- Patent number 9,385,078
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Yannick Feurprier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned via in integrated circuit
- Patent number 9,373,582
- Issue date Jun 21, 2016
- International Business Machines Corporation
- Yannick Feurprier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming interconnect features with reduced sidewall tapering
- Patent number 9,373,543
- Issue date Jun 21, 2016
- GLOBALFOUNDRIES Inc.
- Frank W. Mont
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for top oxide rounding with protection of patterned features
- Patent number 9,252,051
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Joe Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for thinning a bonding wafer
- Patent number 8,476,165
- Issue date Jul 2, 2013
- Tokyo Electron Limited
- Douglas M Trickett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to remove capping layer of insulation dielectric in intercon...
- Patent number 8,202,803
- Issue date Jun 19, 2012
- Tokyo Electron Limited
- Yannick Feurprier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical contacts for integrated circuits and methods of forming...
- Patent number 7,772,110
- Issue date Aug 10, 2010
- Tokyo Electron Limited
- Rodney L. Robison
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Damage-free ashing process and system for post low-k etch
- Patent number 7,279,427
- Issue date Oct 9, 2007
- Tokyo Electron, Ltd.
- Masaru Nishino
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHAMFERLESS VIA STRUCTURES
- Publication number 20190333814
- Publication date Oct 31, 2019
- GLOBALFOUNDRIES INC.
- Mark L. LENHARDT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS VIA STRUCTURES
- Publication number 20190333813
- Publication date Oct 31, 2019
- GLOBALFOUNDRIES INC.
- Mark L. LENHARDT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS VIA STRUCTURES
- Publication number 20180269103
- Publication date Sep 20, 2018
- GLOBALFOUNDRIES INC.
- Mark L. LENHARDT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS VIA STRUCTURES
- Publication number 20170133268
- Publication date May 11, 2017
- GLOBALFOUNDRIES INC.
- Mark L. LENHARDT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS VIA STRUCTURES
- Publication number 20170062275
- Publication date Mar 2, 2017
- International Business Machines Corporation
- Mark L. LENHARDT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS VIA STRUCTURES
- Publication number 20170062331
- Publication date Mar 2, 2017
- International Business Machines Corporation
- Mark L. LENHARDT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF ALIGNED VIA IN INTEGRATED CIRCUIT
- Publication number 20160379929
- Publication date Dec 29, 2016
- International Business Machines Corporation
- Yannick Feurprier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultra-low-k dual damascene structure and method of fabricating
- Publication number 20120064713
- Publication date Mar 15, 2012
- TOKYO ELECTRON LIMITED
- Noel RUSSELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to remove capping layer of insulation dielectric in intercon...
- Publication number 20110143542
- Publication date Jun 16, 2011
- TOKYO ELECTRON LIMITED
- Yannick FEURPRIER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR THINNING A BONDING WAFER
- Publication number 20100255682
- Publication date Oct 7, 2010
- TOKYO ELECTRON LIMITED
- Douglas M. Trickett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL CONTACTS FOR INTEGRATED CIRCUITS AND METHODS OF FORMING...
- Publication number 20090085211
- Publication date Apr 2, 2009
- TOKYO ELECTRON LIMITED
- Rodney L. Robison
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Damage-free ashing process and system for post low-k etch
- Publication number 20070032087
- Publication date Feb 8, 2007
- Masaru Nishino
- H01 - BASIC ELECTRIC ELEMENTS

Douglas M. TRICKETT

Person

Patents Grantslast 30 patents

Chamferless via structures

Chamferless via structures

Chamferless via structures

Chamferless via structures

Chamferless via structures

Self aligned via in integrated circuit

Chamferless via structures

Self aligned via in integrated circuit

Self aligned via in integrated circuit

Forming interconnect features with reduced sidewall tapering

Method for top oxide rounding with protection of patterned features

Method for thinning a bonding wafer

Method to remove capping layer of insulation dielectric in intercon...

Electrical contacts for integrated circuits and methods of forming...

Damage-free ashing process and system for post low-k etch

Patents Applicationslast 30 patents

CHAMFERLESS VIA STRUCTURES

CHAMFERLESS VIA STRUCTURES

CHAMFERLESS VIA STRUCTURES

CHAMFERLESS VIA STRUCTURES

CHAMFERLESS VIA STRUCTURES

CHAMFERLESS VIA STRUCTURES

SELF ALIGNED VIA IN INTEGRATED CIRCUIT

Ultra-low-k dual damascene structure and method of fabricating

Method to remove capping layer of insulation dielectric in intercon...

METHOD FOR THINNING A BONDING WAFER

ELECTRICAL CONTACTS FOR INTEGRATED CIRCUITS AND METHODS OF FORMING...

Damage-free ashing process and system for post low-k etch