Doyle W. Rivers

Person

Rancho Cordova, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques to update a trim parameter in non-volatile memory
- Patent number 11,928,330
- Issue date Mar 12, 2024
- Micron Technology, Inc.
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to update a trim parameter in nonvolatile memory
- Patent number 11,194,472
- Issue date Dec 7, 2021
- Micron Technology, Inc.
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced uncorrectable memory errors
- Patent number 10,936,418
- Issue date Mar 2, 2021
- Intel Corporation
- Kiran Pangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermal monitoring of memory resources
- Patent number 10,678,315
- Issue date Jun 9, 2020
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to update a trim parameter in non-volatile memory
- Patent number 10,649,656
- Issue date May 12, 2020
- Micron Technology, Inc.
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced uncorrectable memory errors
- Patent number 10,324,793
- Issue date Jun 18, 2019
- Intel Corporation
- Kiran Pangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell programming verification
- Patent number 10,325,652
- Issue date Jun 18, 2019
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices, systems, and methods of reducing chip select
- Patent number 10,289,597
- Issue date May 14, 2019
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermal monitoring of memory resources
- Patent number 10,088,880
- Issue date Oct 2, 2018
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Devices, system, and methods for implementing alternate control set...
- Patent number 10,062,444
- Issue date Aug 28, 2018
- Intel Corporation
- Julie M. Walker
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing threshold voltage shift in nonvolatile memory
- Patent number 10,056,139
- Issue date Aug 21, 2018
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices, systems, and methods of reducing chip select
- Patent number 9,996,496
- Issue date Jun 12, 2018
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced uncorrectable memory errors
- Patent number 9,934,088
- Issue date Apr 3, 2018
- Intel Corporation
- Kiran Pangal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Devices, systems, and methods of reducing chip select
- Patent number 9,785,603
- Issue date Oct 10, 2017
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for verifying cell programming in phase change...
- Patent number 9,747,977
- Issue date Aug 29, 2017
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference architecture in a cross-point memory
- Patent number 9,747,978
- Issue date Aug 29, 2017
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing threshold voltage shift in nonvolatile memory
- Patent number 9,721,657
- Issue date Aug 1, 2017
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices, systems, and methods of reducing chip select
- Patent number 9,477,616
- Issue date Oct 25, 2016
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data protection across multiple memory blocks
- Patent number 9,298,545
- Issue date Mar 29, 2016
- Micron Technology, Inc.
- Sampath K. Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Alternate control settings
- Patent number 9,257,162
- Issue date Feb 9, 2016
- Intel Corporation
- Julie M. Walker
- G11 - INFORMATION STORAGE
Information Patent Grant
Drain select gate voltage management
- Patent number 9,230,666
- Issue date Jan 5, 2016
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference architecture in a cross-point memory
- Patent number 9,142,271
- Issue date Sep 22, 2015
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced uncorrectable memory errors
- Patent number 9,136,873
- Issue date Sep 15, 2015
- Intel Corporation
- Kiran Pangal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Isolating, at least in part, local row or column circuitry of memor...
- Patent number 9,030,906
- Issue date May 12, 2015
- Intel Corporation
- Doyle Rivers
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible identification technique
- Patent number 8,982,661
- Issue date Mar 17, 2015
- Intel Corporation
- Julie M. Walker
- G11 - INFORMATION STORAGE
Information Patent Grant
Drain select gate voltage management
- Patent number 8,767,487
- Issue date Jul 1, 2014
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND step up voltage switching method
- Patent number 8,730,736
- Issue date May 20, 2014
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Data protection across multiple memory blocks
- Patent number 8,732,557
- Issue date May 20, 2014
- Micron Technology, Inc.
- Sampath K. Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing effects of erase disturb in a memory device
- Patent number 8,565,018
- Issue date Oct 22, 2013
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND step up voltage switching method
- Patent number 8,441,860
- Issue date May 14, 2013
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY
- Publication number 20220057939
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY
- Publication number 20200241751
- Publication date Jul 30, 2020
- Micron Technology, Inc.
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED UNCORRECTABLE MEMORY ERRORS
- Publication number 20190370112
- Publication date Dec 5, 2019
- Intel Corporation
- Kiran PANGAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY
- Publication number 20190205030
- Publication date Jul 4, 2019
- Micron Technology, Inc.
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMAL MONITORING OF MEMORY RESOURCES
- Publication number 20190107871
- Publication date Apr 11, 2019
- Intel Corporation
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT
- Publication number 20180329854
- Publication date Nov 15, 2018
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED UNCORRECTABLE MEMORY ERRORS
- Publication number 20180253355
- Publication date Sep 6, 2018
- Intel Corporation
- Kiran PANGAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CELL PROGRAMMING VERIFICATION
- Publication number 20180068720
- Publication date Mar 8, 2018
- Intel Corporation
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING THRESHOLD VOLTAGE SHIFT IN NONVOLATILE MEMORY
- Publication number 20170372780
- Publication date Dec 28, 2017
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT
- Publication number 20170351637
- Publication date Dec 7, 2017
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMAL MONITORING OF MEMORY RESOURCES
- Publication number 20170060202
- Publication date Mar 2, 2017
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT
- Publication number 20160328353
- Publication date Nov 10, 2016
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALTERNATE CONTROL SETTINGS
- Publication number 20160260499
- Publication date Sep 8, 2016
- Intel Corporation
- Julie M. Walker
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED UNCORRECTABLE MEMORY ERRORS
- Publication number 20160188409
- Publication date Jun 30, 2016
- Intel Corporation
- Kiran Pangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY
- Publication number 20160093375
- Publication date Mar 31, 2016
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT
- Publication number 20150046611
- Publication date Feb 12, 2015
- Micron Technology, Inc.
- Doyle Rivers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE IDENTIFICATION TECHNIQUE
- Publication number 20140362657
- Publication date Dec 11, 2014
- Julie M. Walker
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS
- Publication number 20140325316
- Publication date Oct 30, 2014
- Micron Technology, Inc.
- Sampath K. Ratnam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAIN SELECT GATE VOLTAGE MANAGEMENT
- Publication number 20140313825
- Publication date Oct 23, 2014
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
CELL PROGRAMMING VERIFICATION
- Publication number 20140269045
- Publication date Sep 18, 2014
- Daniel J. Chu
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED UNCORRECTABLE MEMORY ERRORS
- Publication number 20140258804
- Publication date Sep 11, 2014
- Kiran Pangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISOLATING, AT LEAST IN PART, LOCAL ROW OR COLUMN CIRCUITRY OF MEMOR...
- Publication number 20140016406
- Publication date Jan 16, 2014
- Doyle Rivers
- G11 - INFORMATION STORAGE
Information Patent Application
ALTERNATE CONTROL SETTINGS
- Publication number 20130336040
- Publication date Dec 19, 2013
- Julie M. Walker
- G11 - INFORMATION STORAGE
Information Patent Application
NAND STEP UP VOLTAGE SWITCHING METHOD
- Publication number 20130250679
- Publication date Sep 26, 2013
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS
- Publication number 20120311406
- Publication date Dec 6, 2012
- Micron Technology, Inc.
- Sampath K. Ratnam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
- Publication number 20120236640
- Publication date Sep 20, 2012
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
NAND STEP UP VOLTAGE SWITCHING METHOD
- Publication number 20120140567
- Publication date Jun 7, 2012
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
DRAIN SELECT GATE VOLTAGE MANAGEMENT
- Publication number 20110216600
- Publication date Sep 8, 2011
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
- Publication number 20110128782
- Publication date Jun 2, 2011
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
NAND STEP VOLTAGE SWITCHING METHOD
- Publication number 20100128529
- Publication date May 27, 2010
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE

Doyle W. Rivers

Person

Patents Grantslast 30 patents

Techniques to update a trim parameter in non-volatile memory

Techniques to update a trim parameter in nonvolatile memory

Reduced uncorrectable memory errors

Thermal monitoring of memory resources

Techniques to update a trim parameter in non-volatile memory

Reduced uncorrectable memory errors

Cell programming verification

Devices, systems, and methods of reducing chip select

Thermal monitoring of memory resources

Devices, system, and methods for implementing alternate control set...

Managing threshold voltage shift in nonvolatile memory

Devices, systems, and methods of reducing chip select

Reduced uncorrectable memory errors

Devices, systems, and methods of reducing chip select

Methods and systems for verifying cell programming in phase change...

Reference architecture in a cross-point memory

Managing threshold voltage shift in nonvolatile memory

Devices, systems, and methods of reducing chip select

Data protection across multiple memory blocks

Alternate control settings

Drain select gate voltage management

Reference architecture in a cross-point memory

Reduced uncorrectable memory errors

Isolating, at least in part, local row or column circuitry of memor...

Flexible identification technique

Drain select gate voltage management

NAND step up voltage switching method

Data protection across multiple memory blocks

Reducing effects of erase disturb in a memory device

NAND step up voltage switching method

Patents Applicationslast 30 patents

TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY

TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY

REDUCED UNCORRECTABLE MEMORY ERRORS

TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY

THERMAL MONITORING OF MEMORY RESOURCES

DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

REDUCED UNCORRECTABLE MEMORY ERRORS

CELL PROGRAMMING VERIFICATION

MANAGING THRESHOLD VOLTAGE SHIFT IN NONVOLATILE MEMORY

DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

THERMAL MONITORING OF MEMORY RESOURCES

DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

ALTERNATE CONTROL SETTINGS

REDUCED UNCORRECTABLE MEMORY ERRORS

REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY

DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

FLEXIBLE IDENTIFICATION TECHNIQUE

DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS

DRAIN SELECT GATE VOLTAGE MANAGEMENT

CELL PROGRAMMING VERIFICATION

REDUCED UNCORRECTABLE MEMORY ERRORS

ISOLATING, AT LEAST IN PART, LOCAL ROW OR COLUMN CIRCUITRY OF MEMOR...

ALTERNATE CONTROL SETTINGS

NAND STEP UP VOLTAGE SWITCHING METHOD

DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS

REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE

NAND STEP UP VOLTAGE SWITCHING METHOD

DRAIN SELECT GATE VOLTAGE MANAGEMENT

REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE

NAND STEP VOLTAGE SWITCHING METHOD