DREW G. DOBLAR

Person

SAN JOSE, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 11,304,311
- Issue date Apr 12, 2022
- Sanmina Corporation
- Shinichi Iketani
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Delay circuitry to hold up power to a mass storage device and metho...
- Patent number 10,901,851
- Issue date Jan 26, 2021
- Sanmina Corporation
- Paul Batcheller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 10,820,427
- Issue date Oct 27, 2020
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Serial link voltage margin determination in mission mode
- Patent number 8,599,909
- Issue date Dec 3, 2013
- Oracle International Corporation
- Drew G. Doblar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for system energy use management of current shared power sup...
- Patent number 8,595,534
- Issue date Nov 26, 2013
- Oracle International Corporation
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency when activating a power supply unit
- Patent number 8,543,848
- Issue date Sep 24, 2013
- Oracle International Corporation
- Michael Bushue
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Power and area efficient SerDes transmitter
- Patent number 8,542,764
- Issue date Sep 24, 2013
- Sun Microsystems, Inc.
- Dong J. Yoon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Autonomous control in current share power supplies
- Patent number 8,513,831
- Issue date Aug 20, 2013
- Oracle International Corporation
- Michael Bushue
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Real-time optimization of TX FIR filter for high-speed data communi...
- Patent number 8,452,829
- Issue date May 28, 2013
- Oracle America, Inc.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for reducing duty cycle distortion amplification...
- Patent number 8,446,985
- Issue date May 21, 2013
- Oracle America, Inc.
- Drew G. Doblar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mechanism for constructing an oversampled waveform for a set of sig...
- Patent number 8,249,188
- Issue date Aug 21, 2012
- Oracle America, Inc.
- Deqiang Song
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low jitter and high bandwidth clock data recovery
- Patent number 8,249,199
- Issue date Aug 21, 2012
- Oracle America, Inc.
- Drew G. Doblar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Analog baud rate clock and data recovery
- Patent number 8,243,866
- Issue date Aug 14, 2012
- Oracle America, Inc.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Extraction of component models from PCB channel scattering paramete...
- Patent number 8,234,096
- Issue date Jul 31, 2012
- Oracle America, Inc.
- Juyoung Lee
- G01 - MEASURING TESTING
Information Patent Grant
Integrated equalization and CDR adaptation engine with single error...
- Patent number 8,229,020
- Issue date Jul 24, 2012
- Oracle America, Inc.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Use of emphasis to equalize high speed signal quality
- Patent number 8,229,048
- Issue date Jul 24, 2012
- Oracle America, Inc.
- Gabriel C. Risk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method of adapting precursor tap coefficient
- Patent number 8,218,702
- Issue date Jul 10, 2012
- Oracle America, Inc.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Asymmetric decision feedback equalization slicing in high speed tra...
- Patent number 8,155,214
- Issue date Apr 10, 2012
- Oracle America, Inc.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Voltage regulator attach for high current chip applications
- Patent number 8,018,738
- Issue date Sep 13, 2011
- Oracle America, Inc.,
- Drew G. Doblar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Printed circuit board with optimized mounting holes and alignment pins
- Patent number 8,014,159
- Issue date Sep 6, 2011
- Oracle America, Inc.
- Drew G. Doblar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for equalizing a high speed serial data link
- Patent number 8,009,763
- Issue date Aug 30, 2011
- Oracle America, Inc.
- Gabriel Risk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mechanism for constructing an oversampled waveform for a set of sig...
- Patent number 8,000,426
- Issue date Aug 16, 2011
- Oracle America, Inc.
- Deqiang Song
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Equalizer system having a tunable active inductor
- Patent number 7,880,568
- Issue date Feb 1, 2011
- Oracle America, Inc.
- Arif A. Amin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Eye diagram determination during system operation
- Patent number 7,822,110
- Issue date Oct 26, 2010
- Oracle America, Inc.
- Drew G. Doblar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory system including independent isolated power for each memory...
- Patent number 7,779,285
- Issue date Aug 17, 2010
- Oracle America, Inc.
- Drew G. Doblar
- G11 - INFORMATION STORAGE
Information Patent Grant
Reliable startup and steady-state of estimation based CDR and DFE
- Patent number 7,636,408
- Issue date Dec 22, 2009
- Sun Microsystems, Inc.
- Jason H. Bau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Computer system including network slices that map to field replacea...
- Patent number 7,607,069
- Issue date Oct 20, 2009
- Sun Microsystems, Inc.
- Robert E. Cypher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System memory board subsystem using DRAM with integrated high speed...
- Patent number 7,533,212
- Issue date May 12, 2009
- Sun Microsystems, Inc.
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System memory board subsystem using DRAM with stacked dedicated hig...
- Patent number 7,409,491
- Issue date Aug 5, 2008
- Sun Microsystems, Inc.
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Centerplaneless computer system
- Patent number 7,296,106
- Issue date Nov 13, 2007
- Sun Microsystems, Inc.
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...
- Publication number 20210153360
- Publication date May 20, 2021
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...
- Publication number 20200015364
- Publication date Jan 9, 2020
- Sanmina Corporation
- Shinichi Iketani
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
DELAY CIRCUITRY TO HOLD UP POWER TO A MASS STORAGE DEVICE AND METHO...
- Publication number 20180322011
- Publication date Nov 8, 2018
- Sanmina Corporation
- Paul Batcheller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SYSTEM ENERGY USE MANAGEMENT OF CURRENT SHARED POWER SUP...
- Publication number 20120072754
- Publication date Mar 22, 2012
- Oracle International Corporation
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS CONTROL IN CURRENT SHARE POWER SUPPLIES
- Publication number 20120068544
- Publication date Mar 22, 2012
- Oracle International Corporation
- Michael Bushue
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
REDUCING LATENCY WHEN ACTIVATING A POWER SUPPLY UNIT
- Publication number 20120072738
- Publication date Mar 22, 2012
- Oracle International Corporation
- Michael Bushue
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
SERIAL LINK VOLTAGE MARGIN DETERMINATION IN MISSION MODE
- Publication number 20120033685
- Publication date Feb 9, 2012
- Oracle International Corporation
- Drew G. Doblar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIG...
- Publication number 20110261900
- Publication date Oct 27, 2011
- ORACLE AMERICA, INC.
- Deqiang Song
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Voltage Margin Monitoring for an ADC-Based Serializer/Deserializer...
- Publication number 20110150060
- Publication date Jun 23, 2011
- SUN MICROSYSTEMS, INC.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Extraction of Component Models from PCB Channel Scattering Paramete...
- Publication number 20110107292
- Publication date May 5, 2011
- SUN MICROSYSTEMS, INC.
- Juyoung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC DECISION FEEDBACK EQUALIZATION SLICING IN HIGH SPEED TRA...
- Publication number 20110103458
- Publication date May 5, 2011
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PRINTED CIRCUIT BOARD WITH OPTIMIZED MOUNTING HOLES AND ALIGNMENT PINS
- Publication number 20100271793
- Publication date Oct 28, 2010
- SUN MICROSYSTEMS, INC.
- Drew G. Doblar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
AN INTEGRATED EQUALIZATION AND CDR ADAPTATION ENGINE WITH SINGLE ER...
- Publication number 20100238993
- Publication date Sep 23, 2010
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD OF ADAPTING PRECURSOR TAP COEFFICIENT
- Publication number 20100208855
- Publication date Aug 19, 2010
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Power and Area Efficient SerDes Transmitter
- Publication number 20100177841
- Publication date Jul 15, 2010
- Dong J. Yoon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and System for Reducing Duty Cycle Distortion Amplification...
- Publication number 20100158182
- Publication date Jun 24, 2010
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW JITTER AND HIGH BANDWIDTH CLOCK DATA RECOVERY
- Publication number 20100158177
- Publication date Jun 24, 2010
- SUN MICROSYSTEMS, INC.
- Drew G. Doblar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Real-Time Optimization of TX FIR Filter for High-Speed Data Communi...
- Publication number 20090316727
- Publication date Dec 24, 2009
- SUN MICROSYSTEMS, INC.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
VOLTAGE REGULATOR ATTACH FOR HIGH CURRENT CHIP APPLICATIONS
- Publication number 20090296360
- Publication date Dec 3, 2009
- Drew G. Doblar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD AND APPARATUS FOR EQUALIZING A HIGH SPEED SERIAL DATA LINK
- Publication number 20090252212
- Publication date Oct 8, 2009
- SUN MICROSYSTEMS, INC.
- Gabriel Risk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIG...
- Publication number 20090238318
- Publication date Sep 24, 2009
- Deqiang Song
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ANALOG BAUD RATE CLOCK AND DATA RECOVERY
- Publication number 20090224806
- Publication date Sep 10, 2009
- SUN MICROSYSTEMS, INC.
- Dawei Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EQUALIZER SYSTEM HAVING A TUNABLE ACTIVE INDUCTOR
- Publication number 20090074048
- Publication date Mar 19, 2009
- Arif A. Amin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
USE OF EMPHASIS TO EQUALIZE HIGH SPEED SIGNAL QUALITY
- Publication number 20090074049
- Publication date Mar 19, 2009
- SUN MICROSYSTEMS, INC.
- Gabriel C. Risk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Reliable startup and steady-state of estimation based CDR and DFE
- Publication number 20070280343
- Publication date Dec 6, 2007
- Sun Microsystems, Inc.
- Jason H. Bau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System memory board subsystem using dram with stacked dedicated hig...
- Publication number 20070136537
- Publication date Jun 14, 2007
- Sun Microsystems, Inc.
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Electrical connector for conveying signals between two circuit boards
- Publication number 20040203259
- Publication date Oct 14, 2004
- Sun Microsystems, Inc.
- Drew G. Doblar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory system including independent isolated power for each memory...
- Publication number 20040163002
- Publication date Aug 19, 2004
- Drew G. Doblar
- G11 - INFORMATION STORAGE
Information Patent Application
Memory subsystem including memory modules having multiple banks
- Publication number 20040123016
- Publication date Jun 24, 2004
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Encoded clocks to distribute multiple clock signals to multiple dev...
- Publication number 20040013215
- Publication date Jan 22, 2004
- Sun Microsystems, Inc.
- Drew G. Doblar
- G06 - COMPUTING CALCULATING COUNTING

DREW G. DOBLAR

Person

Patents Grantslast 30 patents

Simultaneous and selective wide gap partitioning of via structures...

Delay circuitry to hold up power to a mass storage device and metho...

Simultaneous and selective wide gap partitioning of via structures...

Serial link voltage margin determination in mission mode

Method for system energy use management of current shared power sup...

Reducing latency when activating a power supply unit

Power and area efficient SerDes transmitter

Autonomous control in current share power supplies

Real-time optimization of TX FIR filter for high-speed data communi...

Method and system for reducing duty cycle distortion amplification...

Mechanism for constructing an oversampled waveform for a set of sig...

Low jitter and high bandwidth clock data recovery

Analog baud rate clock and data recovery

Extraction of component models from PCB channel scattering paramete...

Integrated equalization and CDR adaptation engine with single error...

Use of emphasis to equalize high speed signal quality

System and method of adapting precursor tap coefficient

Asymmetric decision feedback equalization slicing in high speed tra...

Voltage regulator attach for high current chip applications

Printed circuit board with optimized mounting holes and alignment pins

Method and apparatus for equalizing a high speed serial data link

Mechanism for constructing an oversampled waveform for a set of sig...

Equalizer system having a tunable active inductor

Eye diagram determination during system operation

Memory system including independent isolated power for each memory...

Reliable startup and steady-state of estimation based CDR and DFE

Computer system including network slices that map to field replacea...

System memory board subsystem using DRAM with integrated high speed...

System memory board subsystem using DRAM with stacked dedicated hig...

Centerplaneless computer system

Patents Applicationslast 30 patents

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...

DELAY CIRCUITRY TO HOLD UP POWER TO A MASS STORAGE DEVICE AND METHO...

METHOD FOR SYSTEM ENERGY USE MANAGEMENT OF CURRENT SHARED POWER SUP...

AUTONOMOUS CONTROL IN CURRENT SHARE POWER SUPPLIES

REDUCING LATENCY WHEN ACTIVATING A POWER SUPPLY UNIT

SERIAL LINK VOLTAGE MARGIN DETERMINATION IN MISSION MODE

MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIG...

Voltage Margin Monitoring for an ADC-Based Serializer/Deserializer...

Extraction of Component Models from PCB Channel Scattering Paramete...

ASYMMETRIC DECISION FEEDBACK EQUALIZATION SLICING IN HIGH SPEED TRA...

PRINTED CIRCUIT BOARD WITH OPTIMIZED MOUNTING HOLES AND ALIGNMENT PINS

AN INTEGRATED EQUALIZATION AND CDR ADAPTATION ENGINE WITH SINGLE ER...

SYSTEM AND METHOD OF ADAPTING PRECURSOR TAP COEFFICIENT

Power and Area Efficient SerDes Transmitter

Method and System for Reducing Duty Cycle Distortion Amplification...

LOW JITTER AND HIGH BANDWIDTH CLOCK DATA RECOVERY

Real-Time Optimization of TX FIR Filter for High-Speed Data Communi...

VOLTAGE REGULATOR ATTACH FOR HIGH CURRENT CHIP APPLICATIONS

METHOD AND APPARATUS FOR EQUALIZING A HIGH SPEED SERIAL DATA LINK

MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIG...

ANALOG BAUD RATE CLOCK AND DATA RECOVERY

EQUALIZER SYSTEM HAVING A TUNABLE ACTIVE INDUCTOR

USE OF EMPHASIS TO EQUALIZE HIGH SPEED SIGNAL QUALITY

Reliable startup and steady-state of estimation based CDR and DFE

System memory board subsystem using dram with stacked dedicated hig...

Electrical connector for conveying signals between two circuit boards

Memory system including independent isolated power for each memory...

Memory subsystem including memory modules having multiple banks

Encoded clocks to distribute multiple clock signals to multiple dev...