Duane A. Champoux

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Random number generation testing systems and methods
- Patent number 12,135,352
- Issue date Nov 5, 2024
- Advantest Corporation
- Marilyn Kushnick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software directed firmware acceleration
- Patent number 12,055,581
- Issue date Aug 6, 2024
- Advantest Corporation
- Duane Champoux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast address to sector number/offset translation to support odd sec...
- Patent number 11,137,910
- Issue date Oct 5, 2021
- Advantest Corporation
- Duane Champoux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test architecture with an FPGA based test board to simulate a DUT o...
- Patent number 11,009,550
- Issue date May 18, 2021
- Advantest Corporation
- Duane Champoux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart and efficient protocol logic analyzer configured within autom...
- Patent number 10,955,461
- Issue date Mar 23, 2021
- Advantest Corporation
- Linden Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Traffic capture and debugging tools for identifying root causes of...
- Patent number 10,929,260
- Issue date Feb 23, 2021
- Advantest Corporation
- Linden Hsu
- G01 - MEASURING TESTING
Information Patent Grant
Fast parallel CRC determination to support SSD testing
- Patent number 10,884,847
- Issue date Jan 5, 2021
- Advantest Corporation
- Duane Champoux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real-time capture of traffic upon failure for protocol debug
- Patent number 10,379,158
- Issue date Aug 13, 2019
- Advantest Corporation
- Duane Champoux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test architecture with a small form factor test board for rapid pro...
- Patent number 10,288,681
- Issue date May 14, 2019
- Advantest Corporation
- Duane Champoux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit tester with cached vector memories
- Patent number 5,925,145
- Issue date Jul 20, 1999
- Credence Systems Corporation
- Gregory Illes
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit tester with distributed instruction processing
- Patent number 5,894,484
- Issue date Apr 13, 1999
- Credence Systems Corporation
- Gregory Illes
- G01 - MEASURING TESTING
Information Patent Grant
Dual source data distribution system for integrated circuit tester
- Patent number 5,838,694
- Issue date Nov 17, 1998
- Credence Systems Corporation
- Gregory Illes
- G01 - MEASURING TESTING
Information Patent Grant
Virtual channel data distribution system for integrated circuit tester
- Patent number 5,805,610
- Issue date Sep 8, 1998
- Credence Systems Corporation
- Gregory Illes
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Random Number Generation Testing Systems and Methods
- Publication number 20210302496
- Publication date Sep 30, 2021
- Advantest Corporation
- Marilyn Kushnick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE DIRECTED FIRMWARE ACCELERATION
- Publication number 20210116494
- Publication date Apr 22, 2021
- Advantest Corporation
- Duane CHAMPOUX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF HOST BUS ADAPTER TO PROVIDE PROTOCOL FLEXIBILITY IN AUTOMATE...
- Publication number 20210117298
- Publication date Apr 22, 2021
- Advantest Corporation
- Mei-Mei SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-STANDARD SECTOR SIZE SYSTEM SUPPORT FOR SSD TESTING
- Publication number 20200292609
- Publication date Sep 17, 2020
- Duane CHAMPOUX
- G01 - MEASURING TESTING
Information Patent Application
FAST ADDRESS TO SECTOR NUMBER/OFFSET TRANSLATION TO SUPPORT ODD SEC...
- Publication number 20200285390
- Publication date Sep 10, 2020
- Duane CHAMPOUX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMART AND EFFICIENT PROTOCOL LOGIC ANALYZER CONFIGURED WITHIN AUTOM...
- Publication number 20190353696
- Publication date Nov 21, 2019
- Advantest Corporation
- Linden HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAFFIC CAPTURE AND DEBUGGING TOOLS FOR IDENTIFYING ROOT CAUSES OF...
- Publication number 20190354453
- Publication date Nov 21, 2019
- Advantest Corporation
- Linden Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOG POST-PROCESSOR FOR IDENTIFYING ROOT CAUSES OF DEVICE FAILURE DU...
- Publication number 20190278645
- Publication date Sep 12, 2019
- Advantest Corporation
- Linden HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST ARCHITECTURE WITH A SMALL FORM FACTOR TEST BOARD FOR RAPID PRO...
- Publication number 20180267101
- Publication date Sep 20, 2018
- Advantest Corporation
- Duane CHAMPOUX
- G01 - MEASURING TESTING
Information Patent Application
REAL-TIME CAPTURE OF TRAFFIC UPON FAILURE FOR PROTOCOL DEBUG
- Publication number 20180224502
- Publication date Aug 9, 2018
- Advantest Corporation
- Duane CHAMPOUX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST ARCHITECTURE WITH AN FPGA BASED TEST BOARD TO SIMULATE A DUT O...
- Publication number 20180196103
- Publication date Jul 12, 2018
- Duane CHAMPOUX
- G01 - MEASURING TESTING

Duane A. Champoux

Person

Patents Grantslast 30 patents

Random number generation testing systems and methods

Software directed firmware acceleration

Fast address to sector number/offset translation to support odd sec...

Test architecture with an FPGA based test board to simulate a DUT o...

Smart and efficient protocol logic analyzer configured within autom...

Traffic capture and debugging tools for identifying root causes of...

Fast parallel CRC determination to support SSD testing

Real-time capture of traffic upon failure for protocol debug

Test architecture with a small form factor test board for rapid pro...

Integrated circuit tester with cached vector memories

Integrated circuit tester with distributed instruction processing

Dual source data distribution system for integrated circuit tester

Virtual channel data distribution system for integrated circuit tester

Patents Applicationslast 30 patents

Random Number Generation Testing Systems and Methods

SOFTWARE DIRECTED FIRMWARE ACCELERATION

USE OF HOST BUS ADAPTER TO PROVIDE PROTOCOL FLEXIBILITY IN AUTOMATE...

NON-STANDARD SECTOR SIZE SYSTEM SUPPORT FOR SSD TESTING

FAST ADDRESS TO SECTOR NUMBER/OFFSET TRANSLATION TO SUPPORT ODD SEC...

SMART AND EFFICIENT PROTOCOL LOGIC ANALYZER CONFIGURED WITHIN AUTOM...

TRAFFIC CAPTURE AND DEBUGGING TOOLS FOR IDENTIFYING ROOT CAUSES OF...

LOG POST-PROCESSOR FOR IDENTIFYING ROOT CAUSES OF DEVICE FAILURE DU...

TEST ARCHITECTURE WITH A SMALL FORM FACTOR TEST BOARD FOR RAPID PRO...

REAL-TIME CAPTURE OF TRAFFIC UPON FAILURE FOR PROTOCOL DEBUG

TEST ARCHITECTURE WITH AN FPGA BASED TEST BOARD TO SIMULATE A DUT O...