Duncan George Elliott

Person

Edmonton, AB, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Level shifter circuits for integrated circuits
- Patent number 8,502,317
- Issue date Aug 6, 2013
- Leendert Jan van den Berg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory sensing with secondary buffer
- Patent number 8,462,574
- Issue date Jun 11, 2013
- Kristopher Chad Breen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a dynamic semiconductor memory with compac...
- Patent number 8,027,212
- Issue date Sep 27, 2011
- Kristopher Chad Breen
- G11 - INFORMATION STORAGE
Information Patent Grant
Alias-locked loop frequency synthesizer using a regenerative sampli...
- Patent number 7,936,192
- Issue date May 3, 2011
- Leendert Jan van den Berg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-layered memory cell structure
- Patent number 7,215,563
- Issue date May 8, 2007
- Tyler L. Brandon
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock logic domino circuits for high-speed and energy efficient mic...
- Patent number 7,123,056
- Issue date Oct 17, 2006
- Mosaid Technologies Incorporated
- Raymond Jit-Hung Sung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for scalable architectures in stackable three-dimensional in...
- Patent number 7,046,522
- Issue date May 16, 2006
- Raymond Jit-Hung Sung
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
System and method for multilevel DRAM sensing and restoring
- Patent number 6,556,469
- Issue date Apr 29, 2003
- Gershom Birk
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Differential Alias-Locked Loop
- Publication number 20200373927
- Publication date Nov 26, 2020
- Jinghang Liang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Sensing With Secondary Buffer
- Publication number 20110310676
- Publication date Dec 22, 2011
- Kristopher Chad Breen
- G11 - INFORMATION STORAGE
Information Patent Application
Level Shifter Circuits For Integrated Circuits
- Publication number 20100201427
- Publication date Aug 12, 2010
- Leendert Jan van den Berg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR MANIPULATING AND DETECTING ANALYTES
- Publication number 20100200781
- Publication date Aug 12, 2010
- Maziyar Khorasani
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
Information Patent Application
Pipelined wordline memory architecture
- Publication number 20090285035
- Publication date Nov 19, 2009
- Tyler Lee Brandon
- G11 - INFORMATION STORAGE
Information Patent Application
Alias-locked loop frequency synthesizer using a regenerative sampli...
- Publication number 20090284286
- Publication date Nov 19, 2009
- Leendert Jan van den Berg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for a dynamic semiconductor memory with compac...
- Publication number 20080219072
- Publication date Sep 11, 2008
- Kristopher Chad Breen
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LAYERED MEMORY CELL STRUCTURE
- Publication number 20050226068
- Publication date Oct 13, 2005
- Tyler L. Brandon
- G11 - INFORMATION STORAGE
Information Patent Application
Ternary content addressable memory directed associative redundancy...
- Publication number 20050081093
- Publication date Apr 14, 2005
- Craig Shannon Joly
- G11 - INFORMATION STORAGE
Information Patent Application
Clock logic domino circuits for high-speed and energy efficient mic...
- Publication number 20040164769
- Publication date Aug 26, 2004
- MOSAID Technologies, Inc.
- Raymond Jit-Hung Sung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Arrayed processing element redundancy architecture
- Publication number 20030179631
- Publication date Sep 25, 2003
- MOSAID Technologies, Inc.
- John Conrad Koob
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for scalable architectures in stackable three-dimentsional i...
- Publication number 20030178228
- Publication date Sep 25, 2003
- Raymond Jit-Hung Sung
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multilevel dram
- Publication number 20020053007
- Publication date May 2, 2002
- Gershom Birk
- G11 - INFORMATION STORAGE

Duncan George Elliott

Person

Patents Grantslast 30 patents

Level shifter circuits for integrated circuits

Memory sensing with secondary buffer

Method and apparatus for a dynamic semiconductor memory with compac...

Alias-locked loop frequency synthesizer using a regenerative sampli...

Multi-layered memory cell structure

Clock logic domino circuits for high-speed and energy efficient mic...

Method for scalable architectures in stackable three-dimensional in...

System and method for multilevel DRAM sensing and restoring

Patents Applicationslast 30 patents

Differential Alias-Locked Loop

Memory Sensing With Secondary Buffer

Level Shifter Circuits For Integrated Circuits

METHOD AND APPARATUS FOR MANIPULATING AND DETECTING ANALYTES

Pipelined wordline memory architecture

Alias-locked loop frequency synthesizer using a regenerative sampli...

Method and apparatus for a dynamic semiconductor memory with compac...

MULTI-LAYERED MEMORY CELL STRUCTURE

Ternary content addressable memory directed associative redundancy...

Clock logic domino circuits for high-speed and energy efficient mic...

Arrayed processing element redundancy architecture

Method for scalable architectures in stackable three-dimentsional i...

Multilevel dram