Dushyant Narayen

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Sunnyvale, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Multi-layer staggered power bus layout design
- Patent number 7,067,859
- Issue date Jun 27, 2006
- LSI Logic Corporation
- Matthew Russell
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Multi-layer staggered power bus layout design
- Publication number 20050046009
- Publication date Mar 3, 2005
- Matthew Russell
- H01 - BASIC ELECTRIC ELEMENTS