Dustin P. WOOD

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit package substrate
- Patent number 10,522,455
- Issue date Dec 31, 2019
- Intel Corporation
- Mathew J. Manusharow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit package substrate
- Patent number 10,242,942
- Issue date Mar 26, 2019
- Intel Corporation
- Mathew J. Manusharow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
iTFC with optimized C(T)
- Patent number 7,755,165
- Issue date Jul 13, 2010
- Intel Corporation
- Cengiz A. Palanduz
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit packages, systems, and methods
- Patent number 7,687,905
- Issue date Mar 30, 2010
- Intel Corporation
- Brent S. Stone
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with improved power signal connection
- Patent number 7,667,320
- Issue date Feb 23, 2010
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
iTFC with optimized C(T)
- Patent number 7,656,644
- Issue date Feb 2, 2010
- Intel Corporation
- Cengiz A. Palanduz
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect shunt used for current distribution and reliability re...
- Patent number 7,524,754
- Issue date Apr 28, 2009
- Intel Corporation
- Mark Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Array capacitors for broadband decoupling applications
- Patent number 7,495,336
- Issue date Feb 24, 2009
- Intel Corporation
- Joel A. Auernheimer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Array capacitors with voids to enable a full-grid socket
- Patent number 7,463,492
- Issue date Dec 9, 2008
- Intel Corporation
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
iTFC with optimized C(T)
- Patent number 7,375,412
- Issue date May 20, 2008
- Intel Corporation
- Cengiz A. Palanduz
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Array capacitor with resistive structure
- Patent number 7,365,428
- Issue date Apr 29, 2008
- Intel Corporation
- Joel A Auernheimer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Array capacitor for decoupling multiple voltage rails
- Patent number 7,355,836
- Issue date Apr 8, 2008
- Intel Corporation
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with improved power signal connection
- Patent number 7,348,214
- Issue date Mar 25, 2008
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit packages, systems, and methods
- Patent number 7,339,263
- Issue date Mar 4, 2008
- Intel Corporation
- Brent S. Stone
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective plating of package terminals
- Patent number 7,321,172
- Issue date Jan 22, 2008
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Array capacitors with voids to enable a full-grid socket
- Patent number 7,265,995
- Issue date Sep 4, 2007
- Intel Corporation
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package with degassing holes
- Patent number 7,243,423
- Issue date Jul 17, 2007
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect shunt used for current distribution and reliability re...
- Patent number 7,208,830
- Issue date Apr 24, 2007
- Intel Corporation
- Mark Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective plating of package terminals
- Patent number 7,186,645
- Issue date Mar 6, 2007
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package with improved power signal connection
- Patent number 7,183,644
- Issue date Feb 27, 2007
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Array capacitor with IC contacts and applications
- Patent number 7,173,804
- Issue date Feb 6, 2007
- Intel Corporation
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate for integrated circuit and method of making the s...
- Patent number 7,152,313
- Issue date Dec 26, 2006
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit packaging architecture
- Patent number 6,979,891
- Issue date Dec 27, 2005
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Metal core integrated circuit package with electrically isolated re...
- Patent number 6,867,491
- Issue date Mar 15, 2005
- Intel Corporation
- John Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package with degassing holes
- Patent number 6,831,233
- Issue date Dec 14, 2004
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multilayer capacitor with multiple plates per layer
- Patent number 6,819,543
- Issue date Nov 16, 2004
- Intel Corporation
- Raymond A. Vieweg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stitched plane structure and process for package power delivery and...
- Patent number 6,501,166
- Issue date Dec 31, 2002
- Intel Corporation
- Dustin Wood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stitched plane structure for package power delivery and dual refere...
- Patent number 6,429,051
- Issue date Aug 6, 2002
- Intel Corporation
- Dustin Wood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package with degassing holes
- Patent number 6,225,687
- Issue date May 1, 2001
- Intel Corporation
- Dustin P. Wood
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUBSTRATE
- Publication number 20190164881
- Publication date May 30, 2019
- Intel Corporation
- Mathew J. MANUSHAROW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SUBSTRATE
- Publication number 20170154842
- Publication date Jun 1, 2017
- Mathew J. MANUSHAROW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PACKAGES, SYSTEMS, AND METHODS
- Publication number 20080142962
- Publication date Jun 19, 2008
- Intel Corporation
- Brent S. Stone
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH IMPROVED POWER SIGNAL CONNECTION
- Publication number 20080136010
- Publication date Jun 12, 2008
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
iTFC WITH OPTIMIZED C(T)
- Publication number 20080106844
- Publication date May 8, 2008
- Cengiz A. Palanduz
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
iTFC WITH OPTIMIZED C(T)
- Publication number 20080106848
- Publication date May 8, 2008
- Cengiz A. Palanduz
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Array capacitors with voids to enable a full-grid socket
- Publication number 20070253142
- Publication date Nov 1, 2007
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Array capacitors for broadband decoupling applications, and methods...
- Publication number 20070152301
- Publication date Jul 5, 2007
- Intel Corporation
- Joel A. Auernheimer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit package with improved power signal connection
- Publication number 20070114675
- Publication date May 24, 2007
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Array capacitor for decoupling multiple voltage rails
- Publication number 20060274479
- Publication date Dec 7, 2006
- Intel Corporation
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermal solution with isolation layer
- Publication number 20060256531
- Publication date Nov 16, 2006
- Intel Corporation
- Ioan Sauciuc
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnect shunt used for current distribution and reliability re...
- Publication number 20060097375
- Publication date May 11, 2006
- Mark Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Array capacitor with resistive structure
- Publication number 20060087030
- Publication date Apr 27, 2006
- Intel Corporation
- Joel A. Auernheimer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Array capacitor with IC contacts and applications
- Publication number 20060067030
- Publication date Mar 30, 2006
- Intel Corporation
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selective plating of package terminals
- Publication number 20060006535
- Publication date Jan 12, 2006
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Interconnect shunt used for current distribution and reliability re...
- Publication number 20060001178
- Publication date Jan 5, 2006
- Mark Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit packages, systems, and methods
- Publication number 20050285243
- Publication date Dec 29, 2005
- Brent S. Stone
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit package with improved power signal connection
- Publication number 20050236707
- Publication date Oct 27, 2005
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Array capacitors with voids to enable a full-grid socket
- Publication number 20050141206
- Publication date Jun 30, 2005
- Kaladhar Radhakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package substrate for integrated circuit and method of making the s...
- Publication number 20050111207
- Publication date May 26, 2005
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Selective plating of package terminals
- Publication number 20050112880
- Publication date May 26, 2005
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Chip package with degassing holes
- Publication number 20050077077
- Publication date Apr 14, 2005
- Intel Corporation
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated circuit packaging architecture
- Publication number 20050051889
- Publication date Mar 10, 2005
- Dustin P. Wood
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTILAYER CAPACITOR WITH MULTIPLE PLATES PER LAYER
- Publication number 20040125540
- Publication date Jul 1, 2004
- Raymond A. Vieweg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal core substrate packaging
- Publication number 20040107569
- Publication date Jun 10, 2004
- John Guzek
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Motherboard power-leveler
- Publication number 20040100780
- Publication date May 27, 2004
- Brent Stone
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Metal core integrated circuit package with electrically isolated re...
- Publication number 20030111710
- Publication date Jun 19, 2003
- John Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stitched plane structure and process for package power delivery and...
- Publication number 20020117744
- Publication date Aug 29, 2002
- Dustin Wood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STITCHED PLANE STRUCTURE FOR PACKAGE POWER DELIVERY AND DUAL REFERE...
- Publication number 20020115238
- Publication date Aug 22, 2002
- Dustin Wood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip package with degassing holes
- Publication number 20010008313
- Publication date Jul 19, 2001
- Intel Corporation
- Dustin P. Wood
- H01 - BASIC ELECTRIC ELEMENTS

Dustin P. WOOD

Person

Patents Grantslast 30 patents

Integrated circuit package substrate

Integrated circuit package substrate

iTFC with optimized C(T)

Integrated circuit packages, systems, and methods

Integrated circuit package with improved power signal connection

iTFC with optimized C(T)

Interconnect shunt used for current distribution and reliability re...

Array capacitors for broadband decoupling applications

Array capacitors with voids to enable a full-grid socket

iTFC with optimized C(T)

Array capacitor with resistive structure

Array capacitor for decoupling multiple voltage rails

Integrated circuit package with improved power signal connection

Integrated circuit packages, systems, and methods

Selective plating of package terminals

Array capacitors with voids to enable a full-grid socket

Chip package with degassing holes

Interconnect shunt used for current distribution and reliability re...

Selective plating of package terminals

Integrated circuit package with improved power signal connection

Array capacitor with IC contacts and applications

Package substrate for integrated circuit and method of making the s...

Integrated circuit packaging architecture

Metal core integrated circuit package with electrically isolated re...

Chip package with degassing holes

Multilayer capacitor with multiple plates per layer

Stitched plane structure and process for package power delivery and...

Stitched plane structure for package power delivery and dual refere...

Chip package with degassing holes

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

INTEGRATED CIRCUIT PACKAGE SUBSTRATE

INTEGRATED CIRCUIT PACKAGES, SYSTEMS, AND METHODS

INTEGRATED CIRCUIT PACKAGE WITH IMPROVED POWER SIGNAL CONNECTION

iTFC WITH OPTIMIZED C(T)

iTFC WITH OPTIMIZED C(T)

Array capacitors with voids to enable a full-grid socket

Array capacitors for broadband decoupling applications, and methods...

Integrated circuit package with improved power signal connection

Array capacitor for decoupling multiple voltage rails

Thermal solution with isolation layer

Interconnect shunt used for current distribution and reliability re...

Array capacitor with resistive structure

Array capacitor with IC contacts and applications

Selective plating of package terminals

Interconnect shunt used for current distribution and reliability re...

Integrated circuit packages, systems, and methods

Integrated circuit package with improved power signal connection

Array capacitors with voids to enable a full-grid socket

Package substrate for integrated circuit and method of making the s...

Selective plating of package terminals

Chip package with degassing holes

Integrated circuit packaging architecture

MULTILAYER CAPACITOR WITH MULTIPLE PLATES PER LAYER

Metal core substrate packaging

Motherboard power-leveler

Metal core integrated circuit package with electrically isolated re...

Stitched plane structure and process for package power delivery and...

STITCHED PLANE STRUCTURE FOR PACKAGE POWER DELIVERY AND DUAL REFERE...

Chip package with degassing holes