Ed Seewann

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit having relaxed setup time via reciprocal clock and data gating
- Patent number 7,600,071
- Issue date Oct 6, 2009
- International Business Machines Corporation
- Ed Seewann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
True/complement generator having relaxed setup time via self-resett...
- Patent number 7,501,854
- Issue date Mar 10, 2009
- International Business Machines Corporation
- Ed Seewann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Content addressable memory including a dual mode cycle boundary latch
- Patent number 7,283,404
- Issue date Oct 16, 2007
- International Business Machines Corporation
- Masood Ahmed Khan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for controlling the timing of precharge in a c...
- Patent number 7,167,385
- Issue date Jan 23, 2007
- International Business Machines Corporation
- Yuen Hung Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for selecting operating characteristics of a c...
- Patent number 7,116,569
- Issue date Oct 3, 2006
- International Business Machines Corporation
- Joaquin Hinojosa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance registers for pulsed logic
- Patent number 5,926,487
- Issue date Jul 20, 1999
- International Business Machines Corporation
- Terry Ivan Chappell
- G01 - MEASURING TESTING
Information Patent Grant
Methodology to test pulsed logic circuits in pseudo-static mode
- Patent number 5,748,012
- Issue date May 5, 1998
- International Business Machines Corporation
- Michael Patrick Beakes
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
True/Complement Generator Having Relaxed Setup Time Via Self-Resett...
- Publication number 20080136452
- Publication date Jun 12, 2008
- Ed Seewann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit Having Relaxed Setup Time Via Reciprocal Clock and Data Gating
- Publication number 20080137468
- Publication date Jun 12, 2008
- Ed Seewann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SELECTING OPERATING CHARACTERISTICS OF A C...
- Publication number 20060181909
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Joaquin Hinojosa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Content addressable memory including a dual mode cycle boundary latch
- Publication number 20060181910
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Masood Ahmed Khan
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for controlling the timing of precharge in a c...
- Publication number 20060181908
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Yuen Hung Chan
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Circuit having relaxed setup time via reciprocal clock and data gating

True/complement generator having relaxed setup time via self-resett...

Content addressable memory including a dual mode cycle boundary latch

Method and apparatus for controlling the timing of precharge in a c...

Method and apparatus for selecting operating characteristics of a c...

High performance registers for pulsed logic

Methodology to test pulsed logic circuits in pseudo-static mode

Patents Applicationslast 30 patents

True/Complement Generator Having Relaxed Setup Time Via Self-Resett...

Circuit Having Relaxed Setup Time Via Reciprocal Clock and Data Gating

METHOD AND APPARATUS FOR SELECTING OPERATING CHARACTERISTICS OF A C...

Content addressable memory including a dual mode cycle boundary latch

Method and apparatus for controlling the timing of precharge in a c...