Edgardo F. Klass

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Area-aware test pattern coverage optimization
- Patent number 11,500,019
- Issue date Nov 15, 2022
- Apple Inc.
- Edgardo F. Klass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for switchable logic to recover integrated circ...
- Patent number 11,204,384
- Issue date Dec 21, 2021
- Apple Inc.
- Edgardo F. Klass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power saving with dual-rail supply voltage scheme
- Patent number 9,973,191
- Issue date May 15, 2018
- Apple Inc.
- Edgardo F. Klass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Lockup latch for subthreshold operation
- Patent number 9,503,086
- Issue date Nov 22, 2016
- Apple Inc.
- Edgardo F. Klass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for testing driver writeability strength on an...
- Patent number 8,947,070
- Issue date Feb 3, 2015
- Apple Inc.
- Ashish R. Jain
- G01 - MEASURING TESTING
Information Patent Grant
IR(voltage) drop analysis in integrated circuit timing
- Patent number 8,712,752
- Issue date Apr 29, 2014
- Apple Inc.
- Betty Y. Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and software tool for analyzing and reducing the failure rat...
- Patent number 8,650,527
- Issue date Feb 11, 2014
- Apple Inc.
- Antonietta Oliva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan latch with phase-free scan enable
- Patent number 8,635,503
- Issue date Jan 21, 2014
- Apple Inc.
- Bo Tang
- G01 - MEASURING TESTING
Information Patent Grant
Reducing narrow gate width effects in an integrated circuit design
- Patent number 8,533,645
- Issue date Sep 10, 2013
- Apple Inc.
- Edgardo F. Klass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile method and tool for simulation of aged transistors
- Patent number 8,397,199
- Issue date Mar 12, 2013
- Apple Inc.
- Apurva H. Soni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock gater with test features and low setup time
- Patent number 8,341,578
- Issue date Dec 25, 2012
- Apple Inc.
- Brian J. Campbell
- G01 - MEASURING TESTING
Information Patent Grant
Scan latch with phase-free scan enable
- Patent number 8,332,698
- Issue date Dec 11, 2012
- Apple Inc.
- Bo Tang
- G01 - MEASURING TESTING
Information Patent Grant
Method and software tool for analyzing and reducing the failure rat...
- Patent number 8,327,310
- Issue date Dec 4, 2012
- Apple Inc.
- Antonietta Oliva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency synchronizer circuit
- Patent number 8,305,125
- Issue date Nov 6, 2012
- Apple Inc.
- Bo Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse flop with enhanced scan implementation
- Patent number 8,301,943
- Issue date Oct 30, 2012
- Apple Inc.
- Edgardo F. Klass
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for testing sense amplifier thresholds on an i...
- Patent number 8,154,275
- Issue date Apr 10, 2012
- Apple Inc.
- Ashish R. Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-gating synchronizer
- Patent number 8,134,387
- Issue date Mar 13, 2012
- Apple Inc.
- Bo Tang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for testing driver writeability strength on an...
- Patent number 8,125,211
- Issue date Feb 28, 2012
- Apple Inc.
- Ashish R. Jain
- G01 - MEASURING TESTING
Information Patent Grant
Mechanism for measuring read current variability of SRAM cells
- Patent number 8,027,213
- Issue date Sep 27, 2011
- Apple Inc.
- Ashish R. Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-gating synchronizer
- Patent number 7,977,976
- Issue date Jul 12, 2011
- Apple Inc.
- Bo Tang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for testing level shifter voltage thresholds o...
- Patent number 7,977,998
- Issue date Jul 12, 2011
- Apple Inc.
- Ashish R. Jain
- G01 - MEASURING TESTING
Information Patent Grant
Low latency synchronizer circuit
- Patent number 7,843,244
- Issue date Nov 30, 2010
- Apple Inc.
- Bo Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock gater with test features and low setup time
- Patent number 7,779,372
- Issue date Aug 17, 2010
- Apple Inc.
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for detecting and preventing race condition in ci...
- Patent number 7,461,305
- Issue date Dec 2, 2008
- Sun Microsystems, Inc.
- Edgardo F. Klass
- G01 - MEASURING TESTING
Information Patent Grant
Digital jitter detector
- Patent number 7,454,674
- Issue date Nov 18, 2008
- P.A. Semi, Inc.
- Greg M. Hess
- G01 - MEASURING TESTING
Information Patent Grant
Digital leakage detector that detects transistor leakage current in...
- Patent number 7,411,409
- Issue date Aug 12, 2008
- P.A. Semi, Inc.
- Edgardo F. Klass
- G01 - MEASURING TESTING
Information Patent Grant
Pulsed flop with scan circuitry
- Patent number 7,373,569
- Issue date May 13, 2008
- P.A. Semi, Inc.
- Edgardo F. Klass
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulsed flop with embedded logic
- Patent number 7,319,344
- Issue date Jan 15, 2008
- P.A. Semi, Inc.
- Edgardo F. Klass
- G01 - MEASURING TESTING
Information Patent Grant
Combined multiplex or/flop
- Patent number 7,245,150
- Issue date Jul 17, 2007
- P.A. Semi, Inc.
- Rajat Goel
- G01 - MEASURING TESTING
Information Patent Grant
Conditional precharge design in staticized dynamic flip-flop with c...
- Patent number 7,088,144
- Issue date Aug 8, 2006
- Sun Microsystems, Inc.
- Bo Tang
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
AREA-AWARE TEST PATTERN COVERAGE OPTIMIZATION
- Publication number 20210356523
- Publication date Nov 18, 2021
- Apple Inc.
- Edgardo F. Klass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Saving with Dual-rail Supply Voltage Scheme
- Publication number 20180013432
- Publication date Jan 11, 2018
- Apple Inc.
- Edgardo F. Klass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Latch with Phase-Free Scan Enable
- Publication number 20130067292
- Publication date Mar 14, 2013
- Apple Inc.
- Bo Tang
- G01 - MEASURING TESTING
Information Patent Application
Method and Software Tool for Analyzing and Reducing the Failure Rat...
- Publication number 20130055191
- Publication date Feb 28, 2013
- Apple Inc.
- Antonietta Oliva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Narrow Gate Width Effects in an Integrated Circuit Design
- Publication number 20120274357
- Publication date Nov 1, 2012
- Edgardo F. Klass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IR Drop Analysis in Integrated Circuit Timing
- Publication number 20120215516
- Publication date Aug 23, 2012
- Betty Y. Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR TESTING DRIVER WRITEABILITY STRENGTH ON AN...
- Publication number 20120112736
- Publication date May 10, 2012
- Ashish R. Jain
- G01 - MEASURING TESTING
Information Patent Application
Scan Latch with Phase-Free Scan Enable
- Publication number 20110289372
- Publication date Nov 24, 2011
- Bo Tang
- G01 - MEASURING TESTING
Information Patent Application
Self-Gating Synchronizer
- Publication number 20110285431
- Publication date Nov 24, 2011
- Bo Tang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Versatile Method and Tool for Simulation of Aged Transistors
- Publication number 20110257954
- Publication date Oct 20, 2011
- Apurva H. Soni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pulse Flop with Enhanced Scan Implementation
- Publication number 20110202809
- Publication date Aug 18, 2011
- Edgardo F. Klass
- G01 - MEASURING TESTING
Information Patent Application
LOW LATENCY SYNCHRONIZER CIRCUIT
- Publication number 20110025394
- Publication date Feb 3, 2011
- Bo Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHOD FOR TESTING SENSE AMPLIFIER THRESHOLDS ON AN I...
- Publication number 20110012643
- Publication date Jan 20, 2011
- Ashish R. Jain
- G11 - INFORMATION STORAGE
Information Patent Application
SKEW TOLERANT SCANNABLE MASTER/SLAVE FLIP-FLOP INCLUDING EMBEDDED L...
- Publication number 20110016367
- Publication date Jan 20, 2011
- Bo Tang
- G01 - MEASURING TESTING
Information Patent Application
MECHANISM FOR MEASURING READ CURRENT VARIABILITY OF SRAM CELLS
- Publication number 20100322026
- Publication date Dec 23, 2010
- Ashish R. Jain
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR TESTING DRIVER WRITEABILITY STRENGTH ON AN...
- Publication number 20100308790
- Publication date Dec 9, 2010
- Ashish R. Jain
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR TESTING LEVEL SHIFTER VOLTAGE THRESHOLDS O...
- Publication number 20100308887
- Publication date Dec 9, 2010
- Ashish R. Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock Gater with Test Features and Low Setup Time
- Publication number 20100277219
- Publication date Nov 4, 2010
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Gater with Test Features and Low Setup Time
- Publication number 20080180159
- Publication date Jul 31, 2008
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital jitter detector
- Publication number 20070157057
- Publication date Jul 5, 2007
- P.A. Semi, Inc.
- Greg M. Hess
- G01 - MEASURING TESTING
Information Patent Application
Pulsed flop with embedded logic
- Publication number 20070139073
- Publication date Jun 21, 2007
- P.A. Semi, Inc.
- Edgardo F. Klass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Combined multiplexor/flop
- Publication number 20070139075
- Publication date Jun 21, 2007
- P.A. Semi, Inc.
- Rajat Goel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Wearout compensation mechanism using back bias technique
- Publication number 20070139098
- Publication date Jun 21, 2007
- P.A. Semi, Inc.
- Edgardo F. Klass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Pulsed flop with scan circuitry
- Publication number 20070143647
- Publication date Jun 21, 2007
- P.A. Semi, Inc.
- Edgardo F. Klass
- G01 - MEASURING TESTING
Information Patent Application
Digital leakage detector
- Publication number 20070109006
- Publication date May 17, 2007
- P.A. Semi, Inc.
- Edgardo F. Klass
- G01 - MEASURING TESTING
Information Patent Application
Conditional precharge design in staticized dynamic flip-flop with c...
- Publication number 20060055427
- Publication date Mar 16, 2006
- Sun Microsystems, Inc.
- Bo Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock skew tolerant clocking scheme
- Publication number 20050024110
- Publication date Feb 3, 2005
- Sun Microsystems, Inc.
- Edgardo F. Klass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for clock control of clocked full-rail differential logic ci...
- Publication number 20040066214
- Publication date Apr 8, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCKED FULL-RAIL DIFFERENTIAL LOGIC WITH SENSE AMPLIFIER AND SHUT-OFF
- Publication number 20040036506
- Publication date Feb 26, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clocked full-rail differential logic with shut-off
- Publication number 20040036504
- Publication date Feb 26, 2004
- Sun Microsystems, Inc.
- Swee Yew Choe
- H03 - BASIC ELECTRONIC CIRCUITRY

Edgardo F. Klass

Person

Patents Grantslast 30 patents

Area-aware test pattern coverage optimization

Methods and systems for switchable logic to recover integrated circ...

Power saving with dual-rail supply voltage scheme

Lockup latch for subthreshold operation

Apparatus and method for testing driver writeability strength on an...

IR(voltage) drop analysis in integrated circuit timing

Method and software tool for analyzing and reducing the failure rat...

Scan latch with phase-free scan enable

Reducing narrow gate width effects in an integrated circuit design

Versatile method and tool for simulation of aged transistors

Clock gater with test features and low setup time

Scan latch with phase-free scan enable

Method and software tool for analyzing and reducing the failure rat...

Low latency synchronizer circuit

Pulse flop with enhanced scan implementation

Apparatus and method for testing sense amplifier thresholds on an i...

Self-gating synchronizer

Apparatus and method for testing driver writeability strength on an...

Mechanism for measuring read current variability of SRAM cells

Self-gating synchronizer

Apparatus and method for testing level shifter voltage thresholds o...

Low latency synchronizer circuit

Clock gater with test features and low setup time

System and method for detecting and preventing race condition in ci...

Digital jitter detector

Digital leakage detector that detects transistor leakage current in...

Pulsed flop with scan circuitry

Pulsed flop with embedded logic

Combined multiplex or/flop

Conditional precharge design in staticized dynamic flip-flop with c...

Patents Applicationslast 30 patents

AREA-AWARE TEST PATTERN COVERAGE OPTIMIZATION

Power Saving with Dual-rail Supply Voltage Scheme

Scan Latch with Phase-Free Scan Enable

Method and Software Tool for Analyzing and Reducing the Failure Rat...

Reducing Narrow Gate Width Effects in an Integrated Circuit Design

IR Drop Analysis in Integrated Circuit Timing

APPARATUS AND METHOD FOR TESTING DRIVER WRITEABILITY STRENGTH ON AN...

Scan Latch with Phase-Free Scan Enable

Self-Gating Synchronizer

Versatile Method and Tool for Simulation of Aged Transistors

Pulse Flop with Enhanced Scan Implementation

LOW LATENCY SYNCHRONIZER CIRCUIT

APPARATUS AND METHOD FOR TESTING SENSE AMPLIFIER THRESHOLDS ON AN I...

SKEW TOLERANT SCANNABLE MASTER/SLAVE FLIP-FLOP INCLUDING EMBEDDED L...

MECHANISM FOR MEASURING READ CURRENT VARIABILITY OF SRAM CELLS

APPARATUS AND METHOD FOR TESTING DRIVER WRITEABILITY STRENGTH ON AN...

APPARATUS AND METHOD FOR TESTING LEVEL SHIFTER VOLTAGE THRESHOLDS O...

Clock Gater with Test Features and Low Setup Time

Clock Gater with Test Features and Low Setup Time

Digital jitter detector

Pulsed flop with embedded logic

Combined multiplexor/flop

Wearout compensation mechanism using back bias technique

Pulsed flop with scan circuitry

Digital leakage detector

Conditional precharge design in staticized dynamic flip-flop with c...

Clock skew tolerant clocking scheme

Method for clock control of clocked full-rail differential logic ci...

CLOCKED FULL-RAIL DIFFERENTIAL LOGIC WITH SENSE AMPLIFIER AND SHUT-OFF

Clocked full-rail differential logic with shut-off