Edison H. Chiu

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Monolithic programmable format pixel array
- Patent number 6,107,979
- Issue date Aug 22, 2000
- Texas Instruments Incorporated
- Edison H. Chiu
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Memory cell array for digital spatial light modulator
- Patent number 5,682,174
- Issue date Oct 28, 1997
- Texas Instruments Incorporated
- Edison H. Chiu
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Spatial light modulator having single bit-line dual-latch memory cells
- Patent number 5,670,977
- Issue date Sep 23, 1997
- Texas Instruments Incorporated
- Edison H. Chiu
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Spatial light modulator having redundant memory cells
- Patent number 5,670,976
- Issue date Sep 23, 1997
- Texas Instruments Incorporated
- Edison H. Chiu
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Color palette device having big/little endian interfacing, systems...
- Patent number 5,313,231
- Issue date May 17, 1994
- Texas Instruments Incorporated
- Chenwei J. Yin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate circuits in transition detection input buffers
- Patent number 5,291,078
- Issue date Mar 1, 1994
- Texas Instruments Incorporated
- Chai-Chin Chao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuitry for transferring data from a data bus and temporary regis...
- Patent number 5,222,230
- Issue date Jun 22, 1993
- Texas Instruments Incorporated
- Michael C. Gill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-ahead flag generator
- Patent number 5,021,994
- Issue date Jun 4, 1991
- Texas Instruments Incorporated
- Jy-Der Tai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for assigning priority to read and write requests received c...
- Patent number 4,933,901
- Issue date Jun 12, 1990
- Texas Instruments Incorporated
- Jy-Der Tai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating point processor architecture
- Patent number 4,916,651
- Issue date Apr 10, 1990
- Texas Instruments Incorporated
- Michael C. Gill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Easily cascadable and testable cache memory
- Patent number 4,884,270
- Issue date Nov 28, 1989
- Texas Instruments Incorporated
- Edison H. Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory reset responsive to change in main memory
- Patent number 4,860,262
- Issue date Aug 22, 1989
- Texas Instruments Incorporated
- Edison H. Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed zero power reset circuit for CMOS memory cells
- Patent number 4,858,182
- Issue date Aug 15, 1989
- Texas Instruments Incorporated
- Roland H. Pang
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture for memory multiplexing
- Patent number 4,837,743
- Issue date Jun 6, 1989
- Texas Instruments Incorporated
- Edison H. Chiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Easily cascadable and testable cache memory
- Patent number 4,831,625
- Issue date May 16, 1989
- Texas Instruments Incorporated
- Edison H. Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast real-time arbiter
- Patent number 4,815,039
- Issue date Mar 21, 1989
- Texas Instruments Incorporated
- Jy-Der Tai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated FET circuit to reduce switching noise
- Patent number 4,789,793
- Issue date Dec 6, 1988
- Texas Instruments Incorporated
- George J. Ehni
- H03 - BASIC ELECTRONIC CIRCUITRY

Edison H. Chiu

Person

Patents Grantslast 30 patents

Monolithic programmable format pixel array

Memory cell array for digital spatial light modulator

Spatial light modulator having single bit-line dual-latch memory cells

Spatial light modulator having redundant memory cells

Color palette device having big/little endian interfacing, systems...

Gate circuits in transition detection input buffers

Circuitry for transferring data from a data bus and temporary regis...

Look-ahead flag generator

Method for assigning priority to read and write requests received c...

Floating point processor architecture

Easily cascadable and testable cache memory

Cache memory reset responsive to change in main memory

High speed zero power reset circuit for CMOS memory cells

Architecture for memory multiplexing

Easily cascadable and testable cache memory

Fast real-time arbiter

Integrated FET circuit to reduce switching noise