Edmund J. Gieske

Person

Cedar Park, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Area-optimized row hammer mitigation
- Patent number 12,182,413
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Sujeet Ayyapureddi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Practical and efficient row hammer error detection
- Patent number 12,119,043
- Issue date Oct 15, 2024
- Micron Technology, Inc.
- Edmund Gieske
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache-assisted row hammer mitigation
- Patent number 12,073,090
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Edmund Gieske
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device security and row hammer mitigation
- Patent number 12,067,270
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Yang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory media row activation-biased caching
- Patent number 11,994,990
- Issue date May 28, 2024
- Micron Technology, Inc.
- Edmund Gieske
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Execution elision of intermediate instruction by processor
- Patent number 11,537,402
- Issue date Dec 27, 2022
- International Business Machines Corporation
- Brian D. Barrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch filter table for storing moderately-confident entries evic...
- Patent number 11,520,588
- Issue date Dec 6, 2022
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store prefetches for dependent loads in a processor
- Patent number 11,481,219
- Issue date Oct 25, 2022
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid and aggregrate branch prediction system with a tagged branch...
- Patent number 11,416,257
- Issue date Aug 16, 2022
- International Business Machines Corporation
- Naga P. Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction address based data prediction and prefetching
- Patent number 11,194,575
- Issue date Dec 7, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fractional or partial line usage prediction in a processor
- Patent number 11,182,161
- Issue date Nov 23, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically adjusting prefetch depth
- Patent number 11,163,683
- Issue date Nov 2, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Limiting table-of-contents prefetching consequent to symbol table r...
- Patent number 11,016,900
- Issue date May 25, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gating updates to branch predictors to reduce pollution from infreq...
- Patent number 10,956,164
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Naga Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Splitting load hit store table for out-of-order processor
- Patent number 10,942,743
- Issue date Mar 9, 2021
- International Business Machines Corporation
- Ehsan Fatehi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Splitting load hit store table for out-of-order processor
- Patent number 10,725,783
- Issue date Jul 28, 2020
- International Business Machines Corporation
- Ehsan Fatehi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for utilizing translation lookaside buffer entry numbers...
- Patent number 8,984,254
- Issue date Mar 17, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical error correction for large memories
- Patent number 8,677,205
- Issue date Mar 18, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Ravindraraj Ramaraju
- G11 - INFORMATION STORAGE
Information Patent Grant
Branch target buffer addressing in a data processor
- Patent number 8,458,447
- Issue date Jun 4, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION
- Publication number 20240411466
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Yang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOOM FILTER INTEGRATION INTO A CONTROLLER
- Publication number 20240036762
- Publication date Feb 1, 2024
- Micron Technology, Inc.
- Edmund J. Gieske
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE ROW HAMMER MITIGATION
- Publication number 20240038291
- Publication date Feb 1, 2024
- Micron Technology, Inc.
- Edmund J. Gieske
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION
- Publication number 20230393770
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Yang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS
- Publication number 20230395126
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Edmund J. Gieske
- G11 - INFORMATION STORAGE
Information Patent Application
FINITE TIME COUNTING PERIOD COUNTING OF INFINITE DATA STREAMS
- Publication number 20230282258
- Publication date Sep 7, 2023
- Micron Technology, Inc.
- Edmund GIESKE
- G11 - INFORMATION STORAGE
Information Patent Application
PRACTICAL AND EFFICIENT ROW HAMMER ERROR DETECTION
- Publication number 20230260565
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Edmund GIESKE
- G11 - INFORMATION STORAGE
Information Patent Application
AREA-OPTIMIZED ROW HAMMER MITIGATION
- Publication number 20230236735
- Publication date Jul 27, 2023
- Micron Technology, Inc.
- Sujeet AYYAPUREDDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE-ASSISTED ROW HAMMER MITIGATION
- Publication number 20230236739
- Publication date Jul 27, 2023
- Micron Technology, Inc.
- Edmund GIESKE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MEDIA ROW ACTIVATION-BIASED CACHING
- Publication number 20230236968
- Publication date Jul 27, 2023
- Micron Technology, Inc.
- Edmund GIESKE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALIASED ROW HAMMER DETECTOR
- Publication number 20230238046
- Publication date Jul 27, 2023
- Micron Technology, Inc.
- Edmund GIESKE
- G11 - INFORMATION STORAGE
Information Patent Application
ROW HAMMER INTERRUPTS TO THE OPERATING SYSTEM
- Publication number 20230237152
- Publication date Jul 27, 2023
- Micron Technology, Inc.
- Sujeet AYYAPUREDDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTION ELISION OF INTERMEDIATE INSTRUCTION BY PROCESSOR
- Publication number 20230028929
- Publication date Jan 26, 2023
- International Business Machines Corporation
- Brian D. Barrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORE PREFETCHES FOR DEPENDENT LOADS IN A PROCESSOR
- Publication number 20210349722
- Publication date Nov 11, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FRACTIONAL OR PARTIAL LINE USAGE PREDICTION IN A PROCESSOR
- Publication number 20210326138
- Publication date Oct 21, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ADDRESS BASED DATA PREDICTION AND PREFETCHING
- Publication number 20210141642
- Publication date May 13, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ADJUSTING PREFETCH DEPTH
- Publication number 20210034529
- Publication date Feb 4, 2021
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH FILTER TABLE
- Publication number 20200387381
- Publication date Dec 10, 2020
- International Business Machines Corporation
- Mohit Karve
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAGGED BRANCH ORIENTATION PREDICTOR
- Publication number 20200326951
- Publication date Oct 15, 2020
- International Business Machines Corporation
- Naga P. GORTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPLITTING LOAD HIT STORE TABLE FOR OUT-OF-ORDER PROCESSOR
- Publication number 20200257535
- Publication date Aug 13, 2020
- International Business Machines Corporation
- Ehsan Fatehi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GATING UPDATES TO BRANCH PREDICTORS TO REDUCE POLLUTION FROM INFREQ...
- Publication number 20200167165
- Publication date May 28, 2020
- International Business Machines Corporation
- Naga Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPLITTING LOAD HIT STORE TABLE FOR OUT-OF-ORDER PROCESSOR
- Publication number 20200142702
- Publication date May 7, 2020
- International Business Machines Corporation
- Ehsan Fatehi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers...
- Publication number 20140095784
- Publication date Apr 3, 2014
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR
- Publication number 20120324209
- Publication date Dec 20, 2012
- Thang M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL ERROR CORRECTION FOR LARGE MEMORIES
- Publication number 20120233498
- Publication date Sep 13, 2012
- Ravindraraj Ramaraju
- G06 - COMPUTING CALCULATING COUNTING

Edmund J. Gieske

Person

Patents Grantslast 30 patents

Area-optimized row hammer mitigation

Practical and efficient row hammer error detection

Cache-assisted row hammer mitigation

Memory device security and row hammer mitigation

Memory media row activation-biased caching

Execution elision of intermediate instruction by processor

Prefetch filter table for storing moderately-confident entries evic...

Store prefetches for dependent loads in a processor

Hybrid and aggregrate branch prediction system with a tagged branch...

Instruction address based data prediction and prefetching

Fractional or partial line usage prediction in a processor

Dynamically adjusting prefetch depth

Limiting table-of-contents prefetching consequent to symbol table r...

Gating updates to branch predictors to reduce pollution from infreq...

Splitting load hit store table for out-of-order processor

Splitting load hit store table for out-of-order processor

Techniques for utilizing translation lookaside buffer entry numbers...

Hierarchical error correction for large memories

Branch target buffer addressing in a data processor

Patents Applicationslast 30 patents

MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION

BLOOM FILTER INTEGRATION INTO A CONTROLLER

SELECTABLE ROW HAMMER MITIGATION

MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION

ROW HAMMER MITIGATION USING HIERARCHICAL DETECTORS

FINITE TIME COUNTING PERIOD COUNTING OF INFINITE DATA STREAMS

PRACTICAL AND EFFICIENT ROW HAMMER ERROR DETECTION

AREA-OPTIMIZED ROW HAMMER MITIGATION

CACHE-ASSISTED ROW HAMMER MITIGATION

MEMORY MEDIA ROW ACTIVATION-BIASED CACHING

ALIASED ROW HAMMER DETECTOR

ROW HAMMER INTERRUPTS TO THE OPERATING SYSTEM

EXECUTION ELISION OF INTERMEDIATE INSTRUCTION BY PROCESSOR

STORE PREFETCHES FOR DEPENDENT LOADS IN A PROCESSOR

FRACTIONAL OR PARTIAL LINE USAGE PREDICTION IN A PROCESSOR

INSTRUCTION ADDRESS BASED DATA PREDICTION AND PREFETCHING

DYNAMICALLY ADJUSTING PREFETCH DEPTH

PREFETCH FILTER TABLE

TAGGED BRANCH ORIENTATION PREDICTOR

SPLITTING LOAD HIT STORE TABLE FOR OUT-OF-ORDER PROCESSOR

GATING UPDATES TO BRANCH PREDICTORS TO REDUCE POLLUTION FROM INFREQ...

SPLITTING LOAD HIT STORE TABLE FOR OUT-OF-ORDER PROCESSOR

Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers...

BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR

HIERARCHICAL ERROR CORRECTION FOR LARGE MEMORIES