Edward Baxter Eichelberger

Person

Hyde Park, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Speed enhanced level shifting circuit utilizing diode capacitance
- Patent number 5,852,367
- Issue date Dec 22, 1998
- International Business Machines Corporation
- David William Boerstler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low signal margin detect circuit
- Patent number 5,396,182
- Issue date Mar 7, 1995
- International Business Machines Corporation
- David W. Boerstler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacitively cross-coupled DCS emitter-follower output stage
- Patent number 5,389,832
- Issue date Feb 14, 1995
- International Business Machines Corporation
- David W. Boerstler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced differential current switch compensating upshift circuit
- Patent number 5,274,285
- Issue date Dec 28, 1993
- International Business Machines Corporation
- David W. Boerstler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power push pull driver
- Patent number 5,124,591
- Issue date Jun 23, 1992
- International Business Machines Corporation
- Francis Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Weighted random pattern testing apparatus and method
- Patent number 4,801,870
- Issue date Jan 31, 1989
- International Business Machines Corporation
- Edward B. Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level differential cascode current switch masterslice
- Patent number 4,760,289
- Issue date Jul 26, 1988
- International Business Machines Corporation
- Edward B. Eichelberger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Weighted random pattern testing apparatus and method
- Patent number 4,745,355
- Issue date May 17, 1988
- International Business Machines Corporation
- Edward B. Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Weighted random pattern testing apparatus and method
- Patent number 4,687,988
- Issue date Aug 18, 1987
- International Business Machines Corporation
- Edward B. Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Random pattern self test design
- Patent number 4,546,473
- Issue date Oct 8, 1985
- International Business Machines Corporation
- Edward B. Eichelberger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of level sensitive testing a functional logic system with em...
- Patent number 4,074,851
- Issue date Feb 21, 1978
- International Business Machines Corporation
- Edward Baxter Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced overhead for clock testing in a level system scan design (L...
- Patent number 4,071,902
- Issue date Jan 31, 1978
- International Business Machines Corporation
- Edward Baxter Eichelberger
- G01 - MEASURING TESTING
Information Patent Grant
Method of propagation delay testing a level sensitive array logic s...
- Patent number 4,063,080
- Issue date Dec 13, 1977
- International Business Machines Corporation
- Edward Baxter Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock generation network for level sensitive logic system
- Patent number 4,063,078
- Issue date Dec 13, 1977
- International Business Machines Corporation
- Sumit Das Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level sensitive embedded array logic system
- Patent number 4,051,352
- Issue date Sep 27, 1977
- International Business Machines Corporation
- Edward Baxter Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High density semiconductor chip organization
- Patent number 4,006,492
- Issue date Feb 1, 1977
- International Business Machines Corporation
- Edward Baxter Eichelberger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance latch circuit
- Patent number 3,986,057
- Issue date Oct 12, 1976
- International Business Machines Corporation
- Edward Baxter Eichelberger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Testing embedded arrays
- Patent number 3,961,252
- Issue date Jun 1, 1976
- International Business Machines Corporation
- Edward B. Eichelberger
- G11 - INFORMATION STORAGE

Edward Baxter Eichelberger

Person

Patents Grantslast 30 patents

Speed enhanced level shifting circuit utilizing diode capacitance

Low signal margin detect circuit

Capacitively cross-coupled DCS emitter-follower output stage

Enhanced differential current switch compensating upshift circuit

Low power push pull driver

Weighted random pattern testing apparatus and method

Two-level differential cascode current switch masterslice

Weighted random pattern testing apparatus and method

Weighted random pattern testing apparatus and method

Random pattern self test design

Method of level sensitive testing a functional logic system with em...

Reduced overhead for clock testing in a level system scan design (L...

Method of propagation delay testing a level sensitive array logic s...

Clock generation network for level sensitive logic system

Level sensitive embedded array logic system

High density semiconductor chip organization

High performance latch circuit

Testing embedded arrays