Edward C. Miller

Person

Eau Claire, WI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Interleaved memory access system having variable-sized segments log...
- Patent number 5,561,784
- Issue date Oct 1, 1996
- Cray Research, Inc.
- Steve S. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing global registers in a multiproce...
- Patent number 5,524,255
- Issue date Jun 4, 1996
- Cray Research, Inc.
- Douglas R. Beard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dedicated centralized signaling mechanism for selectively signaling...
- Patent number 5,239,629
- Issue date Aug 24, 1993
- SuperComputer Systems Limited Partnership
- Edward C. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cluster architecture for a highly parallel scalar/vector multiproce...
- Patent number 5,197,130
- Issue date Mar 23, 1993
- SuperComputer Systems Limited Partnership
- Steve S. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast interrupt mechanism for interrupting processors in parallel in...
- Patent number 5,193,187
- Issue date Mar 9, 1993
- SuperComputer Systems Limited Partnership
- Robert E. Strout
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed architecture for input/output for a multiprocessor system
- Patent number 5,168,547
- Issue date Dec 1, 1992
- SuperComputer Systems Limited Partnership
- Edward C. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global registers for a multiprocessor system
- Patent number 5,165,038
- Issue date Nov 17, 1992
- SuperComputer Systems Limited Partnership
- Douglas R. Beard
- G06 - COMPUTING CALCULATING COUNTING

Edward C. Miller

Person

Patents Grantslast 30 patents

Interleaved memory access system having variable-sized segments log...

Method and apparatus for accessing global registers in a multiproce...

Dedicated centralized signaling mechanism for selectively signaling...

Cluster architecture for a highly parallel scalar/vector multiproce...

Fast interrupt mechanism for interrupting processors in parallel in...

Distributed architecture for input/output for a multiprocessor system

Global registers for a multiprocessor system