Edward Chang

Person

Ft. Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Through-silicon via layout for multi-die integrated circuits
- Patent number 12,107,076
- Issue date Oct 1, 2024
- Advanced Micro Devices, Inc.
- Wonjun Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die stacked power delivery
- Patent number 11,960,339
- Issue date Apr 16, 2024
- Advanced Micro Devices, Inc.
- Eric J. Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In memory logic functions using memory arrays
- Patent number 11,233,510
- Issue date Jan 25, 2022
- Advanced Micro Devices, Inc.
- John J. Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplexer circuit with load balanced fanout characteristics
- Patent number 8,461,902
- Issue date Jun 11, 2013
- Advanced Micro Devices, Inc.
- Josef A. Dvorak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed multiplexing circuit with built-in repeater
- Patent number 7,349,448
- Issue date Mar 25, 2008
- Hewlett-Packard Development Company, L.P.
- Edward Chang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pseudo-NMOS logic having a feedback controller
- Patent number 6,664,813
- Issue date Dec 16, 2003
- Hewlett-Packard Development Company, L.P.
- Michael A McCurdy
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
THROUGH-SILICON VIA LAYOUT FOR MULTI-DIE INTEGRATED CIRCUITS
- Publication number 20230207527
- Publication date Jun 29, 2023
- ADVANCED MICRO DEVICES, INC.
- Wonjun JUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE STACKED POWER DELIVERY
- Publication number 20230009881
- Publication date Jan 12, 2023
- Eric J. Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN MEMORY LOGIC FUNCTIONS USING MEMORY ARRAYS
- Publication number 20190334524
- Publication date Oct 31, 2019
- ADVANCED MICRO DEVICES, INC.
- John J. Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLEXER CIRCUIT WITH LOAD BALANCED FANOUT CHARACTERISTICS
- Publication number 20120194250
- Publication date Aug 2, 2012
- Advanced Micro Devices, Inc.
- Josef A. DVORAK
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Distributed multiplexing circuit with built-in repeater
- Publication number 20050025196
- Publication date Feb 3, 2005
- Edward Chang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pseudo-NMOS logic having a feedback controller
- Publication number 20040095162
- Publication date May 20, 2004
- Michael A. McCurdy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for improving observability of signals interna...
- Publication number 20030204803
- Publication date Oct 30, 2003
- Michael C. Sedmak
- G01 - MEASURING TESTING
Information Patent Application
Pseudo-NMOS logic having a feedback controller
- Publication number 20030179013
- Publication date Sep 25, 2003
- Michael A. McCurdy
- H03 - BASIC ELECTRONIC CIRCUITRY

Edward Chang

Person

Patents Grantslast 30 patents

Through-silicon via layout for multi-die integrated circuits

Multi-die stacked power delivery

In memory logic functions using memory arrays

Multiplexer circuit with load balanced fanout characteristics

Distributed multiplexing circuit with built-in repeater

Pseudo-NMOS logic having a feedback controller

Patents Applicationslast 30 patents

THROUGH-SILICON VIA LAYOUT FOR MULTI-DIE INTEGRATED CIRCUITS

MULTI-DIE STACKED POWER DELIVERY

IN MEMORY LOGIC FUNCTIONS USING MEMORY ARRAYS

MULTIPLEXER CIRCUIT WITH LOAD BALANCED FANOUT CHARACTERISTICS

Distributed multiplexing circuit with built-in repeater

Pseudo-NMOS logic having a feedback controller

Method and apparatus for improving observability of signals interna...

Pseudo-NMOS logic having a feedback controller