Edward Franklin Runnion

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flash memory programming and verification with reduced leakage current
- Patent number 8,031,528
- Issue date Oct 4, 2011
- Spansion LLC
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Applying negative gate voltage to wordlines adjacent to wordline as...
- Patent number 7,995,386
- Issue date Aug 9, 2011
- Spansion LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory programming and verification with reduced leakage current
- Patent number 7,630,253
- Issue date Dec 8, 2009
- Spansion LLC
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Algorithm for charge loss reduction and Vt distribution improvement
- Patent number 7,619,932
- Issue date Nov 17, 2009
- Spansion LLC
- Gwyn Robert Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Cycling improvement using higher erase bias
- Patent number 7,561,471
- Issue date Jul 14, 2009
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramp gate erase for dual bit flash memory
- Patent number 7,319,615
- Issue date Jan 15, 2008
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for reducing the threshold voltage distribution...
- Patent number 7,170,796
- Issue date Jan 30, 2007
- Spansion LLC
- Yi He
- G11 - INFORMATION STORAGE
Information Patent Grant
Pocket implant for complementary bit disturb improvement and chargi...
- Patent number 6,958,272
- Issue date Oct 25, 2005
- Advanced Micro Devices, Inc.
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to obtain temperature independent program threshold voltage...
- Patent number 6,944,057
- Issue date Sep 13, 2005
- FASL LLC
- Edward F. Runnion
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for erasing a nitride memory device
- Patent number 6,906,959
- Issue date Jun 14, 2005
- Advanced Micro Devices, Inc.
- Mark W. Randolph
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and methods of using negative gate stress to correct...
- Patent number 6,834,012
- Issue date Dec 21, 2004
- Advanced Micro Devices, Inc.
- Yi He
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of controlling program threshold voltage distribution of a d...
- Patent number 6,822,909
- Issue date Nov 23, 2004
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-charge method for reading a non-volatile memory cell
- Patent number 6,788,583
- Issue date Sep 7, 2004
- Advanced Micro Devices, Inc.
- Yi He
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming a dual cell memory device
- Patent number 6,775,187
- Issue date Aug 10, 2004
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reading a non-volatile memory cell adjacent to an inacti...
- Patent number 6,771,545
- Issue date Aug 3, 2004
- Advanced Micro Devices Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of improving dynamic reference tracking for flash memory unit
- Patent number 6,735,114
- Issue date May 11, 2004
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...
- Publication number 20100128521
- Publication date May 27, 2010
- SPANSION LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT
- Publication number 20100027350
- Publication date Feb 4, 2010
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Application
ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT
- Publication number 20090154251
- Publication date Jun 18, 2009
- SPANSION LLC
- Gwyn Robert Jones
- G11 - INFORMATION STORAGE
Information Patent Application
Cycling improvement using higher erase bias
- Publication number 20080151644
- Publication date Jun 26, 2008
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Application
RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY
- Publication number 20080037330
- Publication date Feb 14, 2008
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory programming and verification with reduced leakage current
- Publication number 20070237003
- Publication date Oct 11, 2007
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Application
Pocket implant for complementary bit disturb improvement and chargi...
- Publication number 20050153508
- Publication date Jul 14, 2005
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and system for erasing a nitride memory device
- Publication number 20040169218
- Publication date Sep 2, 2004
- Mark W. Randolph
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL
- Publication number 20040105312
- Publication date Jun 3, 2004
- Yi He
- G11 - INFORMATION STORAGE

Edward Franklin Runnion

Person

Patents Grantslast 30 patents

Flash memory programming and verification with reduced leakage current

Applying negative gate voltage to wordlines adjacent to wordline as...

Flash memory programming and verification with reduced leakage current

Algorithm for charge loss reduction and Vt distribution improvement

Cycling improvement using higher erase bias

Ramp gate erase for dual bit flash memory

Methods and systems for reducing the threshold voltage distribution...

Pocket implant for complementary bit disturb improvement and chargi...

Method to obtain temperature independent program threshold voltage...

Method and system for erasing a nitride memory device

Memory device and methods of using negative gate stress to correct...

Method of controlling program threshold voltage distribution of a d...

Pre-charge method for reading a non-volatile memory cell

Method of programming a dual cell memory device

Method for reading a non-volatile memory cell adjacent to an inacti...

Method of improving dynamic reference tracking for flash memory unit

Patents Applicationslast 30 patents

APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...

FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT

ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT

Cycling improvement using higher erase bias

RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY

Flash memory programming and verification with reduced leakage current

Pocket implant for complementary bit disturb improvement and chargi...

Method and system for erasing a nitride memory device

PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL