Edward Hsia

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of determining voltage compensation for flash memory devices
- Patent number 7,440,333
- Issue date Oct 21, 2008
- Spansion LLC
- Ed Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase algorithm for multi-level bit flash memory
- Patent number 7,251,158
- Issue date Jul 31, 2007
- Spansion LLC
- Ed Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi bit program algorithm
- Patent number 7,038,950
- Issue date May 2, 2006
- Spansion LLC
- Darlene Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of determining voltage compensation for flash memory devices
- Patent number 7,009,887
- Issue date Mar 7, 2006
- FASL LLC
- Ed Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method using positive gate stress to recover over...
- Patent number 6,967,873
- Issue date Nov 22, 2005
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming dual cell memory device to store multiple dat...
- Patent number 6,956,768
- Issue date Oct 18, 2005
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase method for a dual bit memory cell
- Patent number 6,901,010
- Issue date May 31, 2005
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of controlling program threshold voltage distribution of a d...
- Patent number 6,822,909
- Issue date Nov 23, 2004
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of determining charge loss activation energy of a memory array
- Patent number 6,813,752
- Issue date Nov 2, 2004
- Advanced Micro Devices, Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory read circuit with end of life simulation
- Patent number 6,791,880
- Issue date Sep 14, 2004
- Fasl, LLC
- Kazuhiro Kurihara
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of dual cell memory device operation for improved end-of-lif...
- Patent number 6,778,442
- Issue date Aug 17, 2004
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming a dual cell memory device
- Patent number 6,775,187
- Issue date Aug 10, 2004
- Advanced Micro Devices, Inc.
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reading a non-volatile memory cell adjacent to an inacti...
- Patent number 6,771,545
- Issue date Aug 3, 2004
- Advanced Micro Devices Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming and reading a dual cell memory device
- Patent number 6,768,673
- Issue date Jul 27, 2004
- Advanced Micro Devices, Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Source drain implant during ONO formation for improved isolation of...
- Patent number 6,436,768
- Issue date Aug 20, 2002
- Advanced Micro Devices, Inc.
- Jean Yee-Mei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of utilizing fast chip erase to screen endurance rejects
- Patent number 6,381,550
- Issue date Apr 30, 2002
- Advanced Micro Devices, Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of screening memory cells at room temperature that would be...
- Patent number 5,870,407
- Issue date Feb 9, 1999
- Advanced Micro Devices, Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of screening hot temperature erase rejects at room temperature
- Patent number 5,751,633
- Issue date May 12, 1998
- Advanced Micro Devices, Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of utilizing redundancy testing to substitute for main array...
- Patent number 5,724,365
- Issue date Mar 3, 1998
- Advanced Micro Devices, Inc.
- Edward Hsia
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method of determining voltage compensation for flash memory devices
- Publication number 20060120151
- Publication date Jun 8, 2006
- Ed Hsia
- G11 - INFORMATION STORAGE
Information Patent Application
Erase algorithm for multi-level bit flash memory
- Publication number 20050276120
- Publication date Dec 15, 2005
- Ed Hsia
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device and method using positive gate stress to recover over...
- Publication number 20050073886
- Publication date Apr 7, 2005
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Application
Method of programming dual cell memory device to store multiple dat...
- Publication number 20040208057
- Publication date Oct 21, 2004
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE

Edward Hsia

Person

Patents Grantslast 30 patents

Method of determining voltage compensation for flash memory devices

Erase algorithm for multi-level bit flash memory

Multi bit program algorithm

Method of determining voltage compensation for flash memory devices

Memory device and method using positive gate stress to recover over...

Method of programming dual cell memory device to store multiple dat...

Erase method for a dual bit memory cell

Method of controlling program threshold voltage distribution of a d...

Method of determining charge loss activation energy of a memory array

Non-volatile memory read circuit with end of life simulation

Method of dual cell memory device operation for improved end-of-lif...

Method of programming a dual cell memory device

Method for reading a non-volatile memory cell adjacent to an inacti...

Method of programming and reading a dual cell memory device

Source drain implant during ONO formation for improved isolation of...

Method of utilizing fast chip erase to screen endurance rejects

Method of screening memory cells at room temperature that would be...

Method of screening hot temperature erase rejects at room temperature

Method of utilizing redundancy testing to substitute for main array...

Patents Applicationslast 30 patents

Method of determining voltage compensation for flash memory devices

Erase algorithm for multi-level bit flash memory

Memory device and method using positive gate stress to recover over...

Method of programming dual cell memory device to store multiple dat...