Edward S. McGettigan

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and methods for reducing clock power in integrated circuits
- Patent number 8,104,012
- Issue date Jan 24, 2012
- Xilinx, Inc.
- Matthew H. Klein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial configuration of a programmable gate array using a bus macr...
- Patent number 7,669,163
- Issue date Feb 23, 2010
- Xilinx, Inc.
- Nicolas John Camilleri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Boundary-scan circuit used for analog and digital testing of an int...
- Patent number 7,102,555
- Issue date Sep 5, 2006
- Xilinx, Inc.
- Anthony J. Collins
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods of utilizing virtual input and output modules i...
- Patent number 7,085,706
- Issue date Aug 1, 2006
- Xilinx, Inc.
- Edward S. McGettigan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial reconfiguration of a programmable gate array using a bus macro
- Patent number 7,024,651
- Issue date Apr 4, 2006
- Xilinx, Inc.
- Nicolas John Camilleri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock template for configuring a programmable gate array
- Patent number 6,732,347
- Issue date May 4, 2004
- Xilinx, Inc.
- Nicolas J. Camilleri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial reconfiguration of a programmable gate array using a bus macro
- Patent number 6,462,579
- Issue date Oct 8, 2002
- Xilinx, Inc.
- Nicolas John Camilleri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic block used as dynamically configurable logic function
- Patent number 6,384,627
- Issue date May 7, 2002
- Xilinx, Inc.
- Bradley K. Fross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loadable up-down counter with asynchronous reset
- Patent number 6,157,209
- Issue date Dec 5, 2000
- Xilinx, Inc.
- Edward S. McGettigan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design implementation of routing in an FPGA using placem...
- Patent number 6,086,629
- Issue date Jul 11, 2000
- Xilinx, Inc.
- Edward S. McGettigan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BOUNDARY-SCAN CIRCUIT USED FOR ANALOG AN DDIGITAL TESTING OF AN INT...
- Publication number 20050242980
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Anthony J. Collins
- G01 - MEASURING TESTING

Edward S. McGettigan

Person

Patents Grantslast 30 patents

System and methods for reducing clock power in integrated circuits

Partial configuration of a programmable gate array using a bus macr...

Boundary-scan circuit used for analog and digital testing of an int...

Systems and methods of utilizing virtual input and output modules i...

Partial reconfiguration of a programmable gate array using a bus macro

Clock template for configuring a programmable gate array

Partial reconfiguration of a programmable gate array using a bus macro

Logic block used as dynamically configurable logic function

Loadable up-down counter with asynchronous reset

Method for design implementation of routing in an FPGA using placem...

Patents Applicationslast 30 patents

BOUNDARY-SCAN CIRCUIT USED FOR ANALOG AN DDIGITAL TESTING OF AN INT...