Edwin M. Fulcher

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-chip package having a contiguous heat spreader assembly
- Patent number 6,963,129
- Issue date Nov 8, 2005
- LSI Logic Corporation
- Thomas Evans
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thick metal top layer
- Patent number 6,867,488
- Issue date Mar 15, 2005
- LSI Logic Corporation
- Edwin M. Fulcher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pads over input circuits
- Patent number 6,828,643
- Issue date Dec 7, 2004
- LSI Logic Corporation
- Edwin M. Fulcher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pad for low k dielectric
- Patent number 6,798,035
- Issue date Sep 28, 2004
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging that uses guard conductors to isolate...
- Patent number 6,791,177
- Issue date Sep 14, 2004
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Ball assignment for ball grid array package
- Patent number 6,762,366
- Issue date Jul 13, 2004
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Isolated stripline structure
- Patent number 6,744,130
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Leah M. Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High density input output
- Patent number 6,671,865
- Issue date Dec 30, 2003
- LSI Logic Corporation
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High density signal routing
- Patent number 6,459,049
- Issue date Oct 1, 2002
- LSI Logic Corporation
- Leah M. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package having signal traces interposed between...
- Patent number 6,008,534
- Issue date Dec 28, 1999
- LSI Logic Corporation
- Edwin M. Fulcher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of assembling ball bump grid array semiconductor packages
- Patent number 5,729,894
- Issue date Mar 24, 1998
- LSI Logic Corporation
- Michael D. Rostoker
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Flip chip package with reduced number of package layers
- Patent number 5,686,764
- Issue date Nov 11, 1997
- LSI Logic Corporation
- Edwin Fulcher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit wafer comprising unsingulated dies, and decoder...
- Patent number 5,648,661
- Issue date Jul 15, 1997
- LSI Logic Corporation
- Michael D. Rostoker
- G11 - INFORMATION STORAGE
Information Patent Grant
Heat sink for semiconductor device assembly
- Patent number 5,311,060
- Issue date May 10, 1994
- LSI Logic Corporation
- Michael D. Rostoker
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Thick metal top layer
- Publication number 20040099884
- Publication date May 27, 2004
- Edwin M. Fulcher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bonding pads over input circuits
- Publication number 20040084742
- Publication date May 6, 2004
- Edwin M. Fulcher
- H01 - BASIC ELECTRIC ELEMENTS

Edwin M. Fulcher

Person

Patents Grantslast 30 patents

Multi-chip package having a contiguous heat spreader assembly

Thick metal top layer

Bonding pads over input circuits

Bonding pad for low k dielectric

Integrated circuit packaging that uses guard conductors to isolate...

Ball assignment for ball grid array package

Isolated stripline structure

High density input output

High density signal routing

Integrated circuit package having signal traces interposed between...

Method of assembling ball bump grid array semiconductor packages

Flip chip package with reduced number of package layers

Integrated circuit wafer comprising unsingulated dies, and decoder...

Heat sink for semiconductor device assembly

Patents Applicationslast 30 patents

Thick metal top layer

Bonding pads over input circuits