Ee Mei Ooi

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Bayan Lepas, MY

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Patents Grantslast 30 patents

Information Patent Grant
Configuration of a programmable device
- Patent number 10,938,620
- Issue date Mar 2, 2021
- Intel Corporation
- Eng Ling Ho
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configuration of a programmable device
- Patent number 10,355,909
- Issue date Jul 16, 2019
- Intel Corporation
- Eng Ling Ho
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory interface circuitry with improved timing margins
- Patent number 9,166,596
- Issue date Oct 20, 2015
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable delay circuitry with compensated delay
- Patent number 8,723,575
- Issue date May 13, 2014
- Altera Corporation
- Ee Mei Ooi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Partial compilation of circuit design with new software version to...
- Patent number 8,245,163
- Issue date Aug 14, 2012
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Segmented Boundary Scan Chain Testing
- Publication number 20240353490
- Publication date Oct 24, 2024
- Ee Mei Ooi
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURATION OF A PROGRAMMABLE DEVICE
- Publication number 20190342141
- Publication date Nov 7, 2019
- Intel Corporation
- Eng Ling Ho
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS
- Publication number 20140145756
- Publication date May 29, 2014
- Altera Corporation
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING