Egor A. Andreev

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Memory that allows simultaneous read requests
- Patent number 6,886,088
- Issue date Apr 26, 2005
- LSI Logic Corporation
- Egor A. Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimal clock timing schedule for an integrated circuit
- Patent number 6,615,397
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Memory that allows simultaneous read requests
- Publication number 20040107308
- Publication date Jun 3, 2004
- Egor A. Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
Optimal clock timing schedule for an integrated circuit
- Publication number 20020091983
- Publication date Jul 11, 2002
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING