Elad RAZ

Person

Ramat Gan, IL

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for sharing a cache line between non-contiguous m...
- Patent number 12,130,736
- Issue date Oct 29, 2024
- Next Silicon Ltd
- Dan Shechter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnected memory grid with bypassable units
- Patent number 12,056,376
- Issue date Aug 6, 2024
- Next Silicon Ltd
- Yoav Lossin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management in a multi-processor environment
- Patent number 12,020,069
- Issue date Jun 25, 2024
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphical user interface for code to dataflow graph representation
- Patent number 11,995,419
- Issue date May 28, 2024
- Next Silicon Ltd
- Oshri Kdoshim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Background processing during remote memory access
- Patent number 11,966,619
- Issue date Apr 23, 2024
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Executing concurrent threads on a reconfigurable processing grid
- Patent number 11,875,153
- Issue date Jan 16, 2024
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for sharing a cache line between non-contiguous m...
- Patent number 11,720,491
- Issue date Aug 8, 2023
- Next Silicon Ltd
- Dan Shechter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable cache architecture and methods for cache coherency
- Patent number 11,720,496
- Issue date Aug 8, 2023
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnected memory grid with bypassable units
- Patent number 11,644,990
- Issue date May 9, 2023
- Next Silicon Ltd
- Yoav Lossin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic allocation of executable code for multiarchitecture heterog...
- Patent number 11,630,669
- Issue date Apr 18, 2023
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing reconfigurable hardware using data sampling
- Patent number 11,294,686
- Issue date Apr 5, 2022
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnected memory grid with bypassable units
- Patent number 11,269,526
- Issue date Mar 8, 2022
- Next Silicon Ltd
- Yoav Lossin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable cache architecture and methods for cache coherency
- Patent number 11,176,041
- Issue date Nov 16, 2021
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Background processing during remote memory access
- Patent number 11,144,238
- Issue date Oct 12, 2021
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic allocation of executable code for multi-architecture hetero...
- Patent number 11,113,059
- Issue date Sep 7, 2021
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Runtime optimization of configurable hardware
- Patent number 10,817,309
- Issue date Oct 27, 2020
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directed and interconnected grid dataflow architecture
- Patent number 10,817,344
- Issue date Oct 27, 2020
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY MANAGEMENT IN A MULTI-PROCESSOR ENVIRONMENT
- Publication number 20240345881
- Publication date Oct 17, 2024
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGEMENT IN A MULTI-PROCESSOR ENVIRONMENT
- Publication number 20240054015
- Publication date Feb 15, 2024
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY AWARE CONTEXT SWITCHING
- Publication number 20240028389
- Publication date Jan 25, 2024
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...
- Publication number 20230393979
- Publication date Dec 7, 2023
- Next Silicon Ltd
- Dan SHECHTER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY
- Publication number 20230376419
- Publication date Nov 23, 2023
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING RECONFIGURABLE HARDWARE USING DATA SAMPLING
- Publication number 20230342157
- Publication date Oct 26, 2023
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS
- Publication number 20230273736
- Publication date Aug 31, 2023
- Next Silicon Ltd
- Yoav LOSSIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ALLOCATION OF EXECUTABLE CODE FOR MULTI-ARCHITECTURE HETERO...
- Publication number 20230229444
- Publication date Jul 20, 2023
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING PARALLEL SOFTWARE THREADS
- Publication number 20230229489
- Publication date Jul 20, 2023
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...
- Publication number 20230195619
- Publication date Jun 22, 2023
- Next Silicon Ltd
- Dan SHECHTER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ALLOCATION OF EXECUTABLE CODE FOR MULTI-ARCHITECTURE HETERO...
- Publication number 20220253312
- Publication date Aug 11, 2022
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BACKGROUND PROCESSING DURING REMOTE MEMORY ACCESS
- Publication number 20220214827
- Publication date Jul 7, 2022
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS
- Publication number 20220155985
- Publication date May 19, 2022
- Next Silicon Ltd
- Yoav LOSSIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY
- Publication number 20220100660
- Publication date Mar 31, 2022
- Next Silicon Ltd
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS
- Publication number 20210334023
- Publication date Oct 28, 2021
- Next Silicon Ltd
- Yoav LOSSIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE
- Publication number 20190079803
- Publication date Mar 14, 2019
- Next Silicon, Ltd.
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RUNTIME OPTIMIZATION OF CONFIGURABLE HARDWARE
- Publication number 20190042282
- Publication date Feb 7, 2019
- Next Silicon, Ltd.
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE LOCKING PRIMITIVE SYSTEM FOR HARDWARE AND METHODS FOR GENE...
- Publication number 20190042332
- Publication date Feb 7, 2019
- Next Silicon, Ltd.
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY
- Publication number 20190042427
- Publication date Feb 7, 2019
- Next Silicon, Ltd.
- Elad RAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and methods thereof for safe compilation of code into embedd...
- Publication number 20150286471
- Publication date Oct 8, 2015
- INTEGRITY PROJECT LTD
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHODS FOR CREDITING PHYSICAL ACTIVITY PERFORMED BY A USER
- Publication number 20150221232
- Publication date Aug 6, 2015
- Go Vivo Ltd.
- Ilan ZIV
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE

Person

Patents Grantslast 30 patents

System and method for sharing a cache line between non-contiguous m...

Interconnected memory grid with bypassable units

Memory management in a multi-processor environment

Graphical user interface for code to dataflow graph representation

Background processing during remote memory access

Executing concurrent threads on a reconfigurable processing grid

System and method for sharing a cache line between non-contiguous m...

Reconfigurable cache architecture and methods for cache coherency

Interconnected memory grid with bypassable units

Dynamic allocation of executable code for multiarchitecture heterog...

Optimizing reconfigurable hardware using data sampling

Interconnected memory grid with bypassable units

Reconfigurable cache architecture and methods for cache coherency

Background processing during remote memory access

Dynamic allocation of executable code for multi-architecture hetero...

Runtime optimization of configurable hardware

Directed and interconnected grid dataflow architecture

Patents Applicationslast 30 patents

MEMORY MANAGEMENT IN A MULTI-PROCESSOR ENVIRONMENT

MEMORY MANAGEMENT IN A MULTI-PROCESSOR ENVIRONMENT

MEMORY AWARE CONTEXT SWITCHING

SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...

RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY

OPTIMIZING RECONFIGURABLE HARDWARE USING DATA SAMPLING

INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS

DYNAMIC ALLOCATION OF EXECUTABLE CODE FOR MULTI-ARCHITECTURE HETERO...

EXTENDING PARALLEL SOFTWARE THREADS

SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...

DYNAMIC ALLOCATION OF EXECUTABLE CODE FOR MULTI-ARCHITECTURE HETERO...

BACKGROUND PROCESSING DURING REMOTE MEMORY ACCESS

INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS

RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY

INTERCONNECTED MEMORY GRID WITH BYPASSABLE UNITS

DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE

RUNTIME OPTIMIZATION OF CONFIGURABLE HARDWARE

HARDWARE LOCKING PRIMITIVE SYSTEM FOR HARDWARE AND METHODS FOR GENE...

RECONFIGURABLE CACHE ARCHITECTURE AND METHODS FOR CACHE COHERENCY

System and methods thereof for safe compilation of code into embedd...

SYSTEM AND METHODS FOR CREDITING PHYSICAL ACTIVITY PERFORMED BY A USER