Elie Torbey

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Built in self test for input/output characterization
- Patent number 7,814,386
- Issue date Oct 12, 2010
- Texas Instruments Incorporated
- John Joseph Seibold
- G01 - MEASURING TESTING
Information Patent Grant
Digital phase-locked loop circuit with reduced phase jitter frequency
- Patent number 6,285,172
- Issue date Sep 4, 2001
- Texas Instruments Incorporated
- Elie Torbey
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BUILT IN SELF TEST FOR INPUT/OUTPUT CHARACTERIZATION
- Publication number 20090113264
- Publication date Apr 30, 2009
- JOHN Joseph SEIBOLD
- G01 - MEASURING TESTING