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Emery O. Sugasawara
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Pleasanton, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Method and apparatus for avoiding dicing chip-outs in integrated ci...
Patent number
7,354,790
Issue date
Apr 8, 2008
LSI Logic Corporation
Parthasarathy Rajagopalan
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Statistical decision system
Patent number
6,782,500
Issue date
Aug 24, 2004
LSI Logic Corporation
Robert J. Madge
G01 - MEASURING TESTING
Information
Patent Grant
Utilizing a technology-independent system description incorporating...
Patent number
6,687,661
Issue date
Feb 3, 2004
LSI Logic Corporation
Stefan Graef
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Test limits based on position
Patent number
6,598,194
Issue date
Jul 22, 2003
LSI Logic Corporation
Robert J. Madge
G01 - MEASURING TESTING
Information
Patent Grant
Corrosion sensitivity structures for vias and contact holes in inte...
Patent number
6,278,129
Issue date
Aug 21, 2001
LSI Logic Corporation
Emery O. Sugasawara
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Reduced voltage quiescent current test methodology for integrated c...
Patent number
6,239,609
Issue date
May 29, 2001
LSI Logic Corporation
Emery O. Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
On-chip misalignment indication
Patent number
6,221,681
Issue date
Apr 24, 2001
LSI Logic Corporation
Emery Sugasawara
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Method of selecting and synthesizing metal interconnect wires in in...
Patent number
6,189,131
Issue date
Feb 13, 2001
LSI Logic Corporation
Stefan Graef
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Performance monitoring circuitry for integrated circuits
Patent number
6,185,706
Issue date
Feb 6, 2001
LSI Logic Corporation
Emery O. Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Process monitor circuitry for integrated circuits
Patent number
6,124,143
Issue date
Sep 26, 2000
LSI Logic Corporation
Emery O. Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Corrosion sensitivity structures for vias and contact holes in inte...
Patent number
6,103,615
Issue date
Aug 15, 2000
LSI Logic Corporation
Emery O. Sugasawara
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Method for estimating quiescent current in integrated circuits
Patent number
6,102,962
Issue date
Aug 15, 2000
LSI Logic Corporation
Emery O. Sugasawara
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Automatic ranging apparatus and method for precise integrated circu...
Patent number
6,101,458
Issue date
Aug 8, 2000
LSI Logic
Emery Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Probe points and markers for critical paths and integrated circuits
Patent number
6,097,884
Issue date
Aug 1, 2000
LSI Logic Corporation
Emery O. Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Removing solder from integrated circuits for failure analysis
Patent number
6,083,848
Issue date
Jul 4, 2000
LSI Logic Corporation
Emery Sugasawara
B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Semiconductor integrated circuit failure analysis using magnetic im...
Patent number
6,064,220
Issue date
May 16, 2000
LSI Logic Corporation
Emery Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Test circuitry for determining the defect density of a semiconducto...
Patent number
6,061,814
Issue date
May 9, 2000
LSI Logic Corporation
Emery O. Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Selectable power supply lines for isolating defects in integrated c...
Patent number
6,043,672
Issue date
Mar 28, 2000
LSI Logic Corporation
Emery O. Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Electro-static discharge protection of CMOS integrated circuits
Patent number
6,043,539
Issue date
Mar 28, 2000
LSI Logic Corporation
Emery Sugasawara
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Current waveform analysis for testing semiconductor devices
Patent number
6,037,796
Issue date
Mar 14, 2000
LSI Logic Corp.
Stefan Graef
G01 - MEASURING TESTING
Information
Patent Grant
Real time quiescent current test limit methodology
Patent number
6,013,533
Issue date
Jan 11, 2000
LSI Logic Corporation
Emery Osamu Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Methods and apparatus for electrical marking of integrated circuits...
Patent number
5,998,853
Issue date
Dec 7, 1999
LSI Logic Corporation
Emery Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
Reticle and method of design to correct pattern for depth of focus...
Patent number
5,972,541
Issue date
Oct 26, 1999
LSI Logic Corporation
Emery O. Sugasawara
G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information
Patent Grant
Yield improvement techniques through layout optimization
Patent number
5,953,518
Issue date
Sep 14, 1999
LSI Logic Corporation
Emery O. Sugasawara
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Semiconductor integrated circuit core probing for failure analysis
Patent number
5,936,876
Issue date
Aug 10, 1999
LSI Logic Corporation
Emery Sugasawara
G01 - MEASURING TESTING
Information
Patent Grant
On-chip misalignment indication
Patent number
5,898,228
Issue date
Apr 27, 1999
LSI Logic Corporation
Emery Sugasawara
H01 - BASIC ELECTRIC ELEMENTS
Patents Applications
last 30 patents
Information
Patent Application
Method and apparatus for avoiding dicing chip-outs in integrated ci...
Publication number
20060160269
Publication date
Jul 20, 2006
LSI Logic Corporation
Parthasarathy Rajagopalan
H01 - BASIC ELECTRIC ELEMENTS