Emmanuel Arene

Person

Biviers, FR

People

Patents Grantslast 30 patents

Information Patent Grant
System for inserting a wire into a semiconductor chip
- Patent number 11,822,309
- Issue date Nov 21, 2023
- PRIMO1D
- Emmanuel Arene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Radiofrequency transmission/reception device
- Patent number 11,502,411
- Issue date Nov 15, 2022
- PRIMO1D
- Gianfranco Andia Vera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for inserting a wire into a groove of a semiconductor chip
- Patent number 11,209,799
- Issue date Dec 28, 2021
- PRIMO1D
- Emmanuel Arene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for joining a micorelectronic chip to a wire element
- Patent number 11,081,466
- Issue date Aug 3, 2021
- PRIMO1D
- Delphine Rolland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming structures that include a relaxed or pseudo-relaxed layer o...
- Patent number 8,173,512
- Issue date May 8, 2012
- Soitec
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming structures that include a relaxed or pseudo-relaxed layer o...
- Patent number 7,919,393
- Issue date Apr 5, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing the surface roughness of a semiconductor wafer
- Patent number 7,883,628
- Issue date Feb 8, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming structures that include a relaxed or pseudo-relaxed layer o...
- Patent number 7,736,988
- Issue date Jun 15, 2010
- S.O.I. Tec Silicon on Insulator Technologies
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a wafer
- Patent number 7,138,325
- Issue date Nov 21, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming structures that include a relaxed or pseudo-relaxed layer o...
- Patent number 7,018,909
- Issue date Mar 28, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP
- Publication number 20220066416
- Publication date Mar 3, 2022
- PRIMO1D
- Emmanuel Arene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RADIOFREQUENCY TRANSMISSION/RECEPTION DEVICE
- Publication number 20200381829
- Publication date Dec 3, 2020
- PRIMO1D
- Gianfranco Andia Vera
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD FOR JOINING A MICORELECTRONIC CHIP TO A WIRE ELEMENT
- Publication number 20200335475
- Publication date Oct 22, 2020
- PRIMO1D
- Delphine Rolland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP,...
- Publication number 20190391560
- Publication date Dec 26, 2019
- Promo1D
- Emmanuel Arene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT CHIP AND INTEGRATED CI...
- Publication number 20190371716
- Publication date Dec 5, 2019
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Mathilde CARTIER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING STRUCTURES THAT INCLUDE A RELAXED OR PSEUDO-RELAXED LAYER O...
- Publication number 20110217825
- Publication date Sep 8, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING STRUCTURES THAT INCLUDE A RELAXED OR PSEUDO-RELAXED LAYER O...
- Publication number 20100210090
- Publication date Aug 19, 2010
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming structures that include a relaxed or pseudo-relaxed layer o...
- Publication number 20060128117
- Publication date Jun 15, 2006
- S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A.
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of reducing the surface roughness of a semiconductor wafer
- Publication number 20060024908
- Publication date Feb 2, 2006
- S.I.O.TEC Silicon on Insulator Technologes S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacturing a wafer
- Publication number 20050277278
- Publication date Dec 15, 2005
- Christophe Maleville
- C30 - CRYSTAL GROWTH
Information Patent Application
Forming structures that include a relaxed or pseudo-relaxed layer o...
- Publication number 20040195656
- Publication date Oct 7, 2004
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a relaxed or pseudo-relaxed useful layer on a su...
- Publication number 20040192067
- Publication date Sep 30, 2004
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS

Emmanuel Arene

Person

Patents Grantslast 30 patents

System for inserting a wire into a semiconductor chip

Radiofrequency transmission/reception device

Method for inserting a wire into a groove of a semiconductor chip

Method for joining a micorelectronic chip to a wire element

Forming structures that include a relaxed or pseudo-relaxed layer o...

Forming structures that include a relaxed or pseudo-relaxed layer o...

Method of reducing the surface roughness of a semiconductor wafer

Forming structures that include a relaxed or pseudo-relaxed layer o...

Method of manufacturing a wafer

Forming structures that include a relaxed or pseudo-relaxed layer o...

Patents Applicationslast 30 patents

METHOD FOR INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP

RADIOFREQUENCY TRANSMISSION/RECEPTION DEVICE

METHOD FOR JOINING A MICORELECTRONIC CHIP TO A WIRE ELEMENT

METHOD FOR INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP,...

METHOD FOR FABRICATING AN INTEGRATED CIRCUIT CHIP AND INTEGRATED CI...

FORMING STRUCTURES THAT INCLUDE A RELAXED OR PSEUDO-RELAXED LAYER O...

FORMING STRUCTURES THAT INCLUDE A RELAXED OR PSEUDO-RELAXED LAYER O...

Forming structures that include a relaxed or pseudo-relaxed layer o...

Method of reducing the surface roughness of a semiconductor wafer

Method of manufacturing a wafer

Forming structures that include a relaxed or pseudo-relaxed layer o...

Method for forming a relaxed or pseudo-relaxed useful layer on a su...