Emmanuel Josse

Person

La Motte Servolex, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method of manufacturing a device with MOS transistors
- Patent number 9,876,032
- Issue date Jan 23, 2018
- STMicroelectronics (Crolles 2) SAS
- Sonarith Chhun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-orientation integrated cell, in particular input/output cell...
- Patent number 9,735,772
- Issue date Aug 15, 2017
- STMicroelectronics S.A.
- Alexandre Dray
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of forming stressed semiconductor layer
- Patent number 9,543,214
- Issue date Jan 10, 2017
- STMicroelectronics S.A.
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of stressing a semiconductor layer
- Patent number 9,318,372
- Issue date Apr 19, 2016
- STMicroelectronics S.A.
- Olivier Nier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming stressed SOI layer
- Patent number 9,305,828
- Issue date Apr 5, 2016
- STMicroelectronics S.A.
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated electronic circuit incorporating a capacitor
- Patent number 7,504,683
- Issue date Mar 17, 2009
- STMicroelectronics S.A.
- Philippe Candelier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a vertical quadruple conduction channel insul...
- Patent number 7,078,764
- Issue date Jul 18, 2006
- STMicroelectronics, S.A.
- Thomas Skotnicki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a vertical insulated gate transistor with low...
- Patent number 6,861,684
- Issue date Mar 1, 2005
- STMicroelectronics S.A.
- Thomas Skotnicki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a vertical quadruple conduction channel insul...
- Patent number 6,746,923
- Issue date Jun 8, 2004
- STMicroelectronics S.A.
- Thomas Skotnicki
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ELECTRICAL CONNECTION AND ITS METHOD OF FABRICATION
- Publication number 20230352513
- Publication date Nov 2, 2023
- STMicroelectronics (Crolles 2) SAS
- Alain INARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMAGING DEVICE
- Publication number 20230317748
- Publication date Oct 5, 2023
- STMicroelectronics (Grenoble 2) SAS
- Jonathan STECKEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLANAR CELL NANOHEATER DESIGN AND CELL ARCHITECTURE FOR PROGRAMMABL...
- Publication number 20230109590
- Publication date Apr 6, 2023
- STMicroelectronics (Crolles 2) SAS
- Marios BARLAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-ORIENTATION INTEGRATED CELL, IN PARTICULAR INPUT/OUTPUT CELL...
- Publication number 20170288664
- Publication date Oct 5, 2017
- STMicroelectronics S.A.
- Alexandre DRAY
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF MANUFACTURING A DEVICE WITH MOS TRANSISTORS
- Publication number 20170117296
- Publication date Apr 27, 2017
- STMicroelectronics (Crolles 2) SAS
- Sonarith Chhun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-ORIENTATION INTEGRATED CELL, IN PARTICULAR INPUT/OUTPUT CELL...
- Publication number 20160134282
- Publication date May 12, 2016
- STMicroelectronics S.A.
- Alexandre DRAY
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF FORMING STRESSED SEMICONDUCTOR LAYER
- Publication number 20150118805
- Publication date Apr 30, 2015
- STMicroelectronics S.A.
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF STRESSING A SEMICONDUCTOR LAYER
- Publication number 20150118823
- Publication date Apr 30, 2015
- STMicroelectronics S.A.
- Olivier Nier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STRESSED SOI LAYER
- Publication number 20150118824
- Publication date Apr 30, 2015
- STMicroelectronics S.A.
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED ELECTRONIC CIRCUIT INCORPORATING A CAPACITOR
- Publication number 20090134441
- Publication date May 28, 2009
- STMicroelectronics S.A.
- Philippe Candellier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated electronic circuit incorporating a capacitor
- Publication number 20070114596
- Publication date May 24, 2007
- STMicroelectronics S.A.
- Philippe Candelier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a vertical quadruple conduction channel insul...
- Publication number 20040266112
- Publication date Dec 30, 2004
- STMicroelectronics S.A.
- Thomas Skotnicki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a vertical insulated gate transistor with low...
- Publication number 20020177265
- Publication date Nov 28, 2002
- STMicroelectronics S.A.
- Thomas Skotnicki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a vertical quadruple conduction channel insul...
- Publication number 20020163027
- Publication date Nov 7, 2002
- STMicroelectronics S.A.
- Thomas Skotnicki
- H01 - BASIC ELECTRIC ELEMENTS

Emmanuel Josse

Person

Patents Grantslast 30 patents

Method of manufacturing a device with MOS transistors

Multi-orientation integrated cell, in particular input/output cell...

Method of forming stressed semiconductor layer

Method of stressing a semiconductor layer

Method of forming stressed SOI layer

Integrated electronic circuit incorporating a capacitor

Method of fabricating a vertical quadruple conduction channel insul...

Method of fabricating a vertical insulated gate transistor with low...

Method of fabricating a vertical quadruple conduction channel insul...

Patents Applicationslast 30 patents

ELECTRICAL CONNECTION AND ITS METHOD OF FABRICATION

IMAGING DEVICE

PLANAR CELL NANOHEATER DESIGN AND CELL ARCHITECTURE FOR PROGRAMMABL...

MULTI-ORIENTATION INTEGRATED CELL, IN PARTICULAR INPUT/OUTPUT CELL...

METHOD OF MANUFACTURING A DEVICE WITH MOS TRANSISTORS

MULTI-ORIENTATION INTEGRATED CELL, IN PARTICULAR INPUT/OUTPUT CELL...

METHOD OF FORMING STRESSED SEMICONDUCTOR LAYER

METHOD OF STRESSING A SEMICONDUCTOR LAYER

METHOD OF FORMING STRESSED SOI LAYER

INTEGRATED ELECTRONIC CIRCUIT INCORPORATING A CAPACITOR

Integrated electronic circuit incorporating a capacitor

Method of fabricating a vertical quadruple conduction channel insul...

Method of fabricating a vertical insulated gate transistor with low...

Method of fabricating a vertical quadruple conduction channel insul...