Emmanuil Lingunis

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory manufacturing process with bitline isolation
- Patent number 8,673,716
- Issue date Mar 18, 2014
- Spansion LLC
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming narrowly spaced flash memory contact openings and...
- Patent number 7,507,661
- Issue date Mar 24, 2009
- Spansion LLC
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with high conductivity region using shallow tr...
- Patent number 7,208,382
- Issue date Apr 24, 2007
- Advanced Micro Devices, Inc.
- Jeffrey P. Erhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment marks with salicided spacers between bitlines for alignme...
- Patent number 7,098,546
- Issue date Aug 29, 2006
- FASL LLC
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
UV-blocking etch stop layer for reducing UV-induced charging of cha...
- Patent number 7,091,088
- Issue date Aug 15, 2006
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed channel
- Patent number 6,963,108
- Issue date Nov 8, 2005
- Advanced Micro Devices, Inc.
- Inkuk Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pocket implant for complementary bit disturb improvement and chargi...
- Patent number 6,958,272
- Issue date Oct 25, 2005
- Advanced Micro Devices, Inc.
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tightly spaced gate formation through damascene process
- Patent number 6,933,219
- Issue date Aug 23, 2005
- Advanced Micro Devices, Inc.
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bitline hard mask spacer flow for memory cell scaling
- Patent number 6,927,145
- Issue date Aug 9, 2005
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a planar structure charge trapping memory cel...
- Patent number 6,855,608
- Issue date Feb 15, 2005
- Advanced Micro Devices, Inc.
- Mark Ramsbey
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory manufacturing process using disposable ARC for wordline form...
- Patent number 6,720,133
- Issue date Apr 13, 2004
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hard mask process for memory device without bitline shorts
- Patent number 6,706,595
- Issue date Mar 16, 2004
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory manufacturing process using bitline rapid thermal anneal
- Patent number 6,653,191
- Issue date Nov 25, 2003
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
RELACS shrink method applied for single print resist mask for LDD o...
- Patent number 6,642,148
- Issue date Nov 4, 2003
- Advanced Micro Devices, Inc.
- Kouros Ghandehari
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory wordline hard mask
- Patent number 6,617,215
- Issue date Sep 9, 2003
- Advanced Micro Devices, Inc.
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making memory wordline hard mask extension
- Patent number 6,479,348
- Issue date Nov 12, 2002
- Advanced Micro Devices, Inc.
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source drain implant during ONO formation for improved isolation of...
- Patent number 6,436,768
- Issue date Aug 20, 2002
- Advanced Micro Devices, Inc.
- Jean Yee-Mei Yang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TR...
- Publication number 20070166938
- Publication date Jul 19, 2007
- Advanced Micro Devices, Inc.
- Jeffrey P. Erhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming narrowly spaced flash memory contact openings and...
- Publication number 20060035459
- Publication date Feb 16, 2006
- Emmanuil H. Lingunis
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Pocket implant for complementary bit disturb improvement and chargi...
- Publication number 20050153508
- Publication date Jul 14, 2005
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
- Publication number 20040014290
- Publication date Jan 22, 2004
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory manufacturing process with bitline isolation
- Publication number 20030190786
- Publication date Oct 9, 2003
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS

Emmanuil Lingunis

Person

Patents Grantslast 30 patents

Memory manufacturing process with bitline isolation

Method of forming narrowly spaced flash memory contact openings and...

Semiconductor device with high conductivity region using shallow tr...

Alignment marks with salicided spacers between bitlines for alignme...

UV-blocking etch stop layer for reducing UV-induced charging of cha...

Recessed channel

Pocket implant for complementary bit disturb improvement and chargi...

Tightly spaced gate formation through damascene process

Bitline hard mask spacer flow for memory cell scaling

Method of fabricating a planar structure charge trapping memory cel...

Memory manufacturing process using disposable ARC for wordline form...

Hard mask process for memory device without bitline shorts

Memory manufacturing process using bitline rapid thermal anneal

RELACS shrink method applied for single print resist mask for LDD o...

Memory wordline hard mask

Method of making memory wordline hard mask extension

Source drain implant during ONO formation for improved isolation of...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TR...

Method of forming narrowly spaced flash memory contact openings and...

Pocket implant for complementary bit disturb improvement and chargi...

HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS

Memory manufacturing process with bitline isolation