Enric Herrero Abellanas

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Cardedeu, ES

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Patents Grantslast 30 patents

Information Patent Grant
Enforcing different operational configurations for different tasks...
- Patent number 9,619,309
- Issue date Apr 11, 2017
- Intel Corporation
- Enric H. Abellanas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Traffic control on an on-chip network
- Patent number 9,608,922
- Issue date Mar 28, 2017
- Intel Corporation
- Matteo Monchiero
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Vulnerability estimation for cache memory
- Patent number 9,075,904
- Issue date Jul 7, 2015
- Intel Corporation
- Javier Carretero Casado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective provision of error correction for memory
- Patent number 9,071,281
- Issue date Jun 30, 2015
- Intel Corporation
- Javier Carretero Casado
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
VULNERABILITY ESTIMATION FOR CACHE MEMORY
- Publication number 20140281740
- Publication date Sep 18, 2014
- Intel Corporation
- Javier Carretero Casado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE PROVISION OF ERROR CORRECTION FOR MEMORY
- Publication number 20140258805
- Publication date Sep 11, 2014
- Javier Carretero Casado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAILURE RATE BASED CONTROL OF PROCESSORS
- Publication number 20140189696
- Publication date Jul 3, 2014
- Enric H. Abellanas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAFFIC CONTROL ON AN ON-CHIP NETWORK
- Publication number 20140010079
- Publication date Jan 9, 2014
- Matteo Monchiero
- G06 - COMPUTING CALCULATING COUNTING