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Enric Herrero
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Cardedeu, ES
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Patents Grants
last 30 patents
Information
Patent Grant
Register error protection through binary translation
Patent number
9,405,647
Issue date
Aug 2, 2016
Intel Corporation
Xavier Vera
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Fault-aware mapping for shared last level cache (LLC)
Patent number
9,286,172
Issue date
Mar 15, 2016
Intel Corporation
Tanausu Ramirez
G11 - INFORMATION STORAGE
Information
Patent Grant
Recovering from data errors using implicit redundancy
Patent number
9,170,947
Issue date
Oct 27, 2015
Intel Corporation
Xavier Vera
Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information
Patent Grant
Content-aware caches for reliability
Patent number
9,112,537
Issue date
Aug 18, 2015
Intel Corporation
Tanausu Ramirez
Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Patents Applications
last 30 patents
Information
Patent Application
TRACKING DISTRIBUTED EXECUTION ON ON-CHIP MULTINODE NETWORKS WITHOU...
Publication number
20140237018
Publication date
Aug 21, 2014
Matteo Monchiero
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
RECOVERING FROM DATA ERRORS USING IMPLICIT REDUNDANCY
Publication number
20140089593
Publication date
Mar 27, 2014
Xavier Vera
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
CONTENT-AWARE CACHES FOR RELIABILITY
Publication number
20140019823
Publication date
Jan 16, 2014
Tanausu Ramirez
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
FAULT-AWARE MAPPING FOR SHARED LAST LEVEL CACHE (LLC)
Publication number
20140006849
Publication date
Jan 2, 2014
Tanausu Ramirez
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION
Publication number
20130318401
Publication date
Nov 28, 2013
Xavier Vera
G06 - COMPUTING CALCULATING COUNTING