Ephrem C. Wu

Person

San Mateo, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shared depthwise convolution
- Patent number 12,159,212
- Issue date Dec 3, 2024
- Xilinx, Inc.
- Ephrem Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable acceleration of reentrant compute operations
- Patent number 12,147,379
- Issue date Nov 19, 2024
- Xilinx, Inc.
- Rajeev Patwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural-network pooling
- Patent number 11,531,869
- Issue date Dec 20, 2022
- Xilinx, Inc.
- Ephrem C. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing consecutive mac operations on a set of data using differ...
- Patent number 11,429,850
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Xiaoqian Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network controller
- Patent number 11,429,851
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Xiaoqian Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linear interpolator of tabulated functions
- Patent number 11,132,296
- Issue date Sep 28, 2021
- Xilinx, Inc.
- Ephrem C. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transfers between a memory and a distributed compute array
- Patent number 11,127,442
- Issue date Sep 21, 2021
- Xilinx, Inc.
- Xiaoqian Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processing block
- Patent number 10,673,438
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Adam Elkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory arrangement for tensor data
- Patent number 10,346,093
- Issue date Jul 9, 2019
- Xilinx, Inc.
- Ephrem C. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked columnar integrated circuits
- Patent number 10,141,938
- Issue date Nov 27, 2018
- Xilinx, Inc.
- Ephrem C. Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Context driven memory circuits
- Patent number 9,858,006
- Issue date Jan 2, 2018
- Xilinx, Inc.
- Ephrem C. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tensor operations and acceleration
- Patent number 9,779,786
- Issue date Oct 3, 2017
- Xilinx, Inc.
- Ephrem C. Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Power control over memory cell arrays
- Patent number 9,666,266
- Issue date May 30, 2017
- Xilinx, Inc.
- Hongbin Ji
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable hardware blocks for time-sharing arithmetic units usin...
- Patent number 9,460,007
- Issue date Oct 4, 2016
- Xilinx, Inc.
- Ephrem C. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-density integrated circuit memory
- Patent number 9,431,095
- Issue date Aug 30, 2016
- Xilinx, Inc.
- Ephrem C. Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Coding using a combinatorial number system
- Patent number 9,378,170
- Issue date Jun 28, 2016
- Xilinx, Inc.
- Ephrem C. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit devices having memory and methods of implementin...
- Patent number 9,153,292
- Issue date Oct 6, 2015
- Xilinx, Inc.
- Ephrem C. Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory matrix
- Patent number 9,083,340
- Issue date Jul 14, 2015
- Xilinx, Inc.
- Ephrem C. Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interposer having an inductor
- Patent number 8,823,133
- Issue date Sep 2, 2014
- Xilinx, Inc.
- Michael O. Jenkins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked die assembly
- Patent number 8,704,384
- Issue date Apr 22, 2014
- Xilinx, Inc.
- Ephrem C. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contention-free memory arrangement
- Patent number 8,611,175
- Issue date Dec 17, 2013
- Xilinx, Inc.
- Ephrem C. Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-die stack package
- Patent number 8,546,955
- Issue date Oct 1, 2013
- Xilinx, Inc.
- Ephrem C. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-protocol gearbox
- Patent number 8,514,634
- Issue date Aug 20, 2013
- Xilinx, Inc.
- Ephrem C. Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Interconnects using self-timed time-division multiplexed bus
- Patent number 8,503,482
- Issue date Aug 6, 2013
- LSI Corporation
- Ting Zhou
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
High speed packet FIFO output buffers for switch fabric with speedup
- Patent number 8,473,657
- Issue date Jun 25, 2013
- LSI Corporation
- Ting Zhou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Security protocol processing for anti-replay protection
- Patent number 8,438,641
- Issue date May 7, 2013
- LSI Corporation
- Vojislav Vukovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multichip module for communications
- Patent number 8,417,867
- Issue date Apr 9, 2013
- Xilinx, Inc.
- Ephrem C. Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet sequence number tracking for an anti-replay window
- Patent number 8,396,985
- Issue date Mar 12, 2013
- LSI Corporation
- Ephrem Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-port memory using single-port memory cells
- Patent number 8,374,050
- Issue date Feb 12, 2013
- LSI Corporation
- Ting Zhou
- G11 - INFORMATION STORAGE
Information Patent Grant
Security association prefetch for security protcol processing
- Patent number 8,359,466
- Issue date Jan 22, 2013
- LSI Corporation
- Sheng Liu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SCALABLE ACCELERATION OF REENTRANT COMPUTE OPERATIONS
- Publication number 20240220444
- Publication date Jul 4, 2024
- Xilinx, Inc.
- Rajeev PATWARI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-DIE NON-BLOCKING CROSSBAR SWITCH
- Publication number 20240205570
- Publication date Jun 20, 2024
- Xilinx, Inc.
- Ephrem WU
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INSTRUCTION GENERATION AND PROGRAMMING MODEL FOR A DATA PROCESSING...
- Publication number 20240069511
- Publication date Feb 29, 2024
- Xilinx, Inc.
- Jorn Tuyls
- G05 - CONTROLLING REGULATING
Information Patent Application
HARDWARE ACCELERATION OF MACHINE LEARNING DESIGNS
- Publication number 20230401480
- Publication date Dec 14, 2023
- Xilinx, Inc.
- Ehsan Ghasemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ACCELERATION OF AFFINE TRANSFORMATIONS
- Publication number 20230077616
- Publication date Mar 16, 2023
- Xilinx, Inc.
- Ephrem WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TRANSFERS BETWEEN A MEMORY AND A DISTRIBUTED COMPUTE ARRAY
- Publication number 20210174848
- Publication date Jun 10, 2021
- Xilinx, Inc.
- Xiaoqian Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING CONSECUTIVE MAC OPERATIONS ON A SET OF DATA USING DIFFER...
- Publication number 20200026989
- Publication date Jan 23, 2020
- Xilinx, Inc.
- Xiaoqian Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED COLUMNAR INTEGRATED CIRCUITS
- Publication number 20180083635
- Publication date Mar 22, 2018
- Xilinx, Inc.
- Ephrem C. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES HAVING MEMORY AND METHODS OF IMPLEMENTIN...
- Publication number 20140254232
- Publication date Sep 11, 2014
- Xilinx, Inc.
- Ephrem C. Wu
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED DIE ASSEMBLY
- Publication number 20130214432
- Publication date Aug 22, 2013
- Xilinx, Inc.
- Ephrem C. Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTENTION-FREE MEMORY ARRANGEMENT
- Publication number 20130148450
- Publication date Jun 13, 2013
- Xilinx, Inc.
- Ephrem C. Wu
- G11 - INFORMATION STORAGE
Information Patent Application
SECURTIY ASSOCIATION PREFETCH FOR SECURITY PROTCOL PROCESSING
- Publication number 20120278615
- Publication date Nov 1, 2012
- LSI CORPORATION
- Sheng Liu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERPOSER HAVING AN INDUCTOR
- Publication number 20120248569
- Publication date Oct 4, 2012
- Xilinx, Inc.
- Michael O. Jenkins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SECURITY PROTOCOL PROCESSING FOR ANTI-REPLAY PROTECTION
- Publication number 20120174216
- Publication date Jul 5, 2012
- Vojislav Vukovic
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTICHIP MODULE FOR COMMUNICATIONS
- Publication number 20120124257
- Publication date May 17, 2012
- Xilinx, Inc.
- Ephrem C. Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PACKET SEQUENCE NUMBER TRACKING FOR AN ANTI-REPLAY WINDOW
- Publication number 20120042096
- Publication date Feb 16, 2012
- LSI CORPORATION
- Ephrem Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multi-Port Memory Using Single-Port Memory Cells
- Publication number 20110310691
- Publication date Dec 22, 2011
- LSI Corporation
- Ting Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnects using Self-timed Time-Division Multiplexed Bus
- Publication number 20110211582
- Publication date Sep 1, 2011
- LSI Corporation
- Ting Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parametric Data-Based Process Monitoring for Adaptive Body Bias Con...
- Publication number 20100333057
- Publication date Dec 30, 2010
- Robin Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffered Crossbar Switch System
- Publication number 20100272117
- Publication date Oct 28, 2010
- LSI CORPORATION
- Ephrem Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH SPEED PACKET FIFO OUTPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP
- Publication number 20100238938
- Publication date Sep 23, 2010
- LSI Corporation
- Ting Zhou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP...
- Publication number 20100238937
- Publication date Sep 23, 2010
- LSI Corporation
- Ting Zhou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW POWER ON-CHIP GLOBAL INTERCONNECTS
- Publication number 20090108925
- Publication date Apr 30, 2009
- Robin Tang
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM FOR AUTOMATIC BANDWIDTH CONTROL OF EQUALIZER ADAPTATION LOOPS
- Publication number 20080304559
- Publication date Dec 11, 2008
- Ephrem C. Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and/or apparatus for link optimization
- Publication number 20070258478
- Publication date Nov 8, 2007
- LSI Logic Corporation
- Ephrem C. Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Connection memory for tributary time-space switches
- Publication number 20060239262
- Publication date Oct 26, 2006
- LSI Logic Corporation
- Ephrem C. Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method of tributary time-space switching
- Publication number 20050030943
- Publication date Feb 10, 2005
- Velio Communications, Inc.
- Ephrem Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital cross-connect
- Publication number 20040062228
- Publication date Apr 1, 2004
- Velio Communications, Inc.
- Ephrem C. Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Non-blocking grooming switch
- Publication number 20030021267
- Publication date Jan 30, 2003
- Velio Communications, Inc.
- Ephrem C. Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Architectures for a single-stage grooming switch
- Publication number 20020181482
- Publication date Dec 5, 2002
- Velio Communications, Inc.
- William J. Dally
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Ephrem C. Wu

Person

Patents Grantslast 30 patents

Shared depthwise convolution

Scalable acceleration of reentrant compute operations

Neural-network pooling

Performing consecutive mac operations on a set of data using differ...

Neural network controller

Linear interpolator of tabulated functions

Data transfers between a memory and a distributed compute array

Digital signal processing block

Memory arrangement for tensor data

Stacked columnar integrated circuits

Context driven memory circuits

Tensor operations and acceleration

Power control over memory cell arrays

Programmable hardware blocks for time-sharing arithmetic units usin...

High-density integrated circuit memory

Coding using a combinatorial number system

Integrated circuit devices having memory and methods of implementin...

Memory matrix

Interposer having an inductor

Stacked die assembly

Contention-free memory arrangement

Multi-die stack package

Multi-protocol gearbox

Interconnects using self-timed time-division multiplexed bus

High speed packet FIFO output buffers for switch fabric with speedup

Security protocol processing for anti-replay protection

Multichip module for communications

Packet sequence number tracking for an anti-replay window

Multi-port memory using single-port memory cells

Security association prefetch for security protcol processing

Patents Applicationslast 30 patents

SCALABLE ACCELERATION OF REENTRANT COMPUTE OPERATIONS

MULTI-DIE NON-BLOCKING CROSSBAR SWITCH

INSTRUCTION GENERATION AND PROGRAMMING MODEL FOR A DATA PROCESSING...

HARDWARE ACCELERATION OF MACHINE LEARNING DESIGNS

HARDWARE ACCELERATION OF AFFINE TRANSFORMATIONS

DATA TRANSFERS BETWEEN A MEMORY AND A DISTRIBUTED COMPUTE ARRAY

PERFORMING CONSECUTIVE MAC OPERATIONS ON A SET OF DATA USING DIFFER...

STACKED COLUMNAR INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DEVICES HAVING MEMORY AND METHODS OF IMPLEMENTIN...

STACKED DIE ASSEMBLY

CONTENTION-FREE MEMORY ARRANGEMENT

SECURTIY ASSOCIATION PREFETCH FOR SECURITY PROTCOL PROCESSING

INTERPOSER HAVING AN INDUCTOR

SECURITY PROTOCOL PROCESSING FOR ANTI-REPLAY PROTECTION

MULTICHIP MODULE FOR COMMUNICATIONS

PACKET SEQUENCE NUMBER TRACKING FOR AN ANTI-REPLAY WINDOW

Multi-Port Memory Using Single-Port Memory Cells

Interconnects using Self-timed Time-Division Multiplexed Bus

Parametric Data-Based Process Monitoring for Adaptive Body Bias Con...

Buffered Crossbar Switch System

HIGH SPEED PACKET FIFO OUTPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP

HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP...

LOW POWER ON-CHIP GLOBAL INTERCONNECTS

SYSTEM FOR AUTOMATIC BANDWIDTH CONTROL OF EQUALIZER ADAPTATION LOOPS

Methods and/or apparatus for link optimization

Connection memory for tributary time-space switches

System and method of tributary time-space switching

Digital cross-connect

Non-blocking grooming switch

Architectures for a single-stage grooming switch