Eran Shifer

Person

Tel Aviv, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Processor having multiple cores, shared core extension logic, and s...
- Patent number 12,086,603
- Issue date Sep 10, 2024
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having multiple cores, shared core extension logic, and s...
- Patent number 11,494,194
- Issue date Nov 8, 2022
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having multiple cores, shared core extension logic, and s...
- Patent number 10,963,263
- Issue date Mar 30, 2021
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having multiple cores, shared core extension logic, and s...
- Patent number 10,901,748
- Issue date Jan 26, 2021
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Management of coherent links and multi-level memory
- Patent number 10,599,568
- Issue date Mar 24, 2020
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic fill policy for a shared cache
- Patent number 10,229,059
- Issue date Mar 12, 2019
- Intel Corporation
- Ayan Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having multiple cores, shared core extension logic, and s...
- Patent number 10,061,593
- Issue date Aug 28, 2018
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid exclusive multi-level memory architecture with memory manage...
- Patent number 9,734,079
- Issue date Aug 15, 2017
- Intel Corporation
- Dannie G. Feekes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having multiple cores, shared core extension logic, and s...
- Patent number 9,582,287
- Issue date Feb 28, 2017
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic priority control based on latency tolerance
- Patent number 8,959,266
- Issue date Feb 17, 2015
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20230052630
- Publication date Feb 16, 2023
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20220004391
- Publication date Jan 6, 2022
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY
- Publication number 20200226066
- Publication date Jul 16, 2020
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20190114176
- Publication date Apr 18, 2019
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT OF COHERENT LINKS AND MULTI-LEVEL MEMORY
- Publication number 20190042425
- Publication date Feb 7, 2019
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20190012178
- Publication date Jan 10, 2019
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC FILL POLICY FOR A SHARED CACHE
- Publication number 20180285261
- Publication date Oct 4, 2018
- Intel Corporation
- Ayan Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT MEMORY AWARE CACHE MANAGEMENT
- Publication number 20180173637
- Publication date Jun 21, 2018
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20170147353
- Publication date May 25, 2017
- lntel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PRIORITY CONTROL BASED ON LATENCY TOLERANCE
- Publication number 20150039790
- Publication date Feb 5, 2015
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID MULTI-LEVEL MEMORY ARCHITECTURE
- Publication number 20150006805
- Publication date Jan 1, 2015
- DANNIE G. FEEKES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20140089635
- Publication date Mar 27, 2014
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Preempting Fixed Function Media Devices
- Publication number 20130307860
- Publication date Nov 21, 2013
- Mostafa Hagog
- G06 - COMPUTING CALCULATING COUNTING

Eran Shifer

Person

Patents Grantslast 30 patents

Processor having multiple cores, shared core extension logic, and s...

Processor having multiple cores, shared core extension logic, and s...

Processor having multiple cores, shared core extension logic, and s...

Processor having multiple cores, shared core extension logic, and s...

Management of coherent links and multi-level memory

Dynamic fill policy for a shared cache

Processor having multiple cores, shared core extension logic, and s...

Hybrid exclusive multi-level memory architecture with memory manage...

Processor having multiple cores, shared core extension logic, and s...

Dynamic priority control based on latency tolerance

Patents Applicationslast 30 patents

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

MANAGEMENT OF COHERENT LINKS AND MULTI-LEVEL MEMORY

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

DYNAMIC FILL POLICY FOR A SHARED CACHE

EFFICIENT MEMORY AWARE CACHE MANAGEMENT

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

DYNAMIC PRIORITY CONTROL BASED ON LATENCY TOLERANCE

HYBRID MULTI-LEVEL MEMORY ARCHITECTURE

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

Preempting Fixed Function Media Devices