ERIC BADI

Person

SAINT LAURENT DU VAR, FR

People

Patents Grantslast 30 patents

Information Patent Grant
12C bus controller slave address register and command FIFO buffer
- Patent number 10,198,382
- Issue date Feb 5, 2019
- Texas Instruments Incorporated
- Frederic Danis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
I2C controller register, control, command and R/W buffer queue logic
- Patent number 9,336,167
- Issue date May 10, 2016
- Texas Instruments Incorporated
- Frederic Danis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock drift compensation applying paired clock compensation values...
- Patent number 9,264,217
- Issue date Feb 16, 2016
- Texas Instruments Incorporated
- Laurent Le-Faucheur
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock drift compensation interpolator adjusting buffer read and wri...
- Patent number 9,014,321
- Issue date Apr 21, 2015
- Texas Instruments Incorporated
- Laurent Le Faucheur
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-latency interface-based networking
- Patent number 8,699,953
- Issue date Apr 15, 2014
- Texas Instruments Incorporated
- Eric Louis Pierre Badi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Micro-sequence based security model
- Patent number 8,190,861
- Issue date May 29, 2012
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing function connected to processor memory hierarchy
- Patent number 8,156,283
- Issue date Apr 10, 2012
- Texas Instruments Incorporated
- Eric L. P. Badi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-clocking memory device
- Patent number 7,234,034
- Issue date Jun 19, 2007
- Texas Instruments Incorporated
- Stephen W. Spriggs
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of operating a memory at high speed using a cycle ready stat...
- Patent number 7,200,730
- Issue date Apr 3, 2007
- Texas Instruments Incorporated
- Bryan D. Sheffield
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelining access to serialization tokens on a bus
- Patent number 7,139,854
- Issue date Nov 21, 2006
- Texas Instruments Incorporated
- Jonathan Y. Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing a memory core multiple times in...
- Patent number 7,035,985
- Issue date Apr 25, 2006
- Texas Instruments Incorporated
- Jean-Marc Bachot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessors
- Patent number 6,658,578
- Issue date Dec 2, 2003
- Texas Instruments Incorporated
- Gilbert Laurenti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing a memory core multiple times in...
- Patent number 6,629,223
- Issue date Sep 30, 2003
- Texas Instruments Incorporated
- Jean-Marc Philippe Bachot
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMMAND QUEUE FOR COMMUNICATION BUS
- Publication number 20160224490
- Publication date Aug 4, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Frederic Danis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR CLOCK DRIFT COMPENSATION INTERPOLATION
- Publication number 20150200771
- Publication date Jul 16, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Laurent Le-Faucheur
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Command Queue for Communications Bus
- Publication number 20140173162
- Publication date Jun 19, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Frederic Danis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Multifunction Serial Link Interface
- Publication number 20140119463
- Publication date May 1, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Yves Michel Marie Masse
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW-LATENCY INTERFACE-BASED NETWORKING
- Publication number 20130252543
- Publication date Sep 26, 2013
- Texas Instruments, Incorporated
- Eric Louis Pierre Badi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR CLOCK DRIFT COMPENSATION INTERPOLATION
- Publication number 20130107930
- Publication date May 2, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Laurent LE FAUCHEUR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROCESSING FUNCTION CONNECTED TO PROCESSOR MEMORY HIERARCHY
- Publication number 20080282033
- Publication date Nov 13, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Eric L. P. BADI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelining access to serialization tokens on a bus
- Publication number 20040255066
- Publication date Dec 16, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Jonathan Y. Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for accessing a memory core multiple times in...
- Publication number 20040109381
- Publication date Jun 10, 2004
- JEAN-MARC BACHOT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self-clocking memory device
- Publication number 20040078510
- Publication date Apr 22, 2004
- Stephen W. Spriggs
- G11 - INFORMATION STORAGE
Information Patent Application
Method of operating a memory at high speed using a cycle ready stat...
- Publication number 20040064661
- Publication date Apr 1, 2004
- Bryan D. Sheffield
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR ACCESSING A MEMORY CORE MULTIPLE TIMES IN...
- Publication number 20030110363
- Publication date Jun 12, 2003
- JEAN-MARC BACHOT
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

12C bus controller slave address register and command FIFO buffer

I2C controller register, control, command and R/W buffer queue logic

Clock drift compensation applying paired clock compensation values...

Clock drift compensation interpolator adjusting buffer read and wri...

Low-latency interface-based networking

Micro-sequence based security model

Processing function connected to processor memory hierarchy

Self-clocking memory device

Method of operating a memory at high speed using a cycle ready stat...

Pipelining access to serialization tokens on a bus

Method and apparatus for accessing a memory core multiple times in...

Microprocessors

Method and apparatus for accessing a memory core multiple times in...

Patents Applicationslast 30 patents

COMMAND QUEUE FOR COMMUNICATION BUS

METHODS AND SYSTEMS FOR CLOCK DRIFT COMPENSATION INTERPOLATION

Command Queue for Communications Bus

Scalable Multifunction Serial Link Interface

LOW-LATENCY INTERFACE-BASED NETWORKING

METHODS AND SYSTEMS FOR CLOCK DRIFT COMPENSATION INTERPOLATION

PROCESSING FUNCTION CONNECTED TO PROCESSOR MEMORY HIERARCHY

Pipelining access to serialization tokens on a bus

Method and apparatus for accessing a memory core multiple times in...

Self-clocking memory device

Method of operating a memory at high speed using a cycle ready stat...

METHOD AND APPARATUS FOR ACCESSING A MEMORY CORE MULTIPLE TIMES IN...