Eric C. Palmer

Person

Tempe, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Passive within via
- Patent number 9,960,079
- Issue date May 1, 2018
- Intel Corporation
- Todd B. Myers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of embedding passive component within via
- Patent number 8,487,446
- Issue date Jul 16, 2013
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Input/output package architectures
- Patent number 8,188,594
- Issue date May 29, 2012
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package on package using a bump-less build up layer (BBUL) package
- Patent number 8,093,704
- Issue date Jan 10, 2012
- Intel Corporation
- Eric C. Palmer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of embedding passive component within via
- Patent number 7,952,202
- Issue date May 31, 2011
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via including multiple electrical paths
- Patent number 7,737,025
- Issue date Jun 15, 2010
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Input/output package architectures, and methods of using same
- Patent number 7,705,447
- Issue date Apr 27, 2010
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of embedding passive component within via
- Patent number 7,275,316
- Issue date Oct 2, 2007
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via including multiple electrical paths
- Patent number 7,183,653
- Issue date Feb 27, 2007
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
PASSIVE WITHIN VIA
- Publication number 20130249112
- Publication date Sep 26, 2013
- Todd B. Myers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA
- Publication number 20110198723
- Publication date Aug 18, 2011
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Input/output package architectures, and methods of using same
- Publication number 20100096743
- Publication date Apr 22, 2010
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INPUT/OUTPUT PACKAGE ARCHITECTURES, AND METHODS OF USING SAME
- Publication number 20100078781
- Publication date Apr 1, 2010
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE
- Publication number 20090294942
- Publication date Dec 3, 2009
- Eric C. Palmer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA
- Publication number 20090057910
- Publication date Mar 5, 2009
- Intel Corporation
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
VIA INCLUDING MULTIPLE ELECTRICAL PATHS
- Publication number 20070117339
- Publication date May 24, 2007
- Intel Corporation
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Passive within via
- Publication number 20050224989
- Publication date Oct 13, 2005
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Via including multiple electrical paths
- Publication number 20050133918
- Publication date Jun 23, 2005
- Intel Corporation
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacked integrated circuit packages and methods of making the packages
- Publication number 20050121769
- Publication date Jun 9, 2005
- Nicholas R. Watts
- H01 - BASIC ELECTRIC ELEMENTS

Eric C. Palmer

Person

Patents Grantslast 30 patents

Passive within via

Method of embedding passive component within via

Input/output package architectures

Package on package using a bump-less build up layer (BBUL) package

Method of embedding passive component within via

Via including multiple electrical paths

Input/output package architectures, and methods of using same

Method of embedding passive component within via

Via including multiple electrical paths

Patents Applicationslast 30 patents

PASSIVE WITHIN VIA

METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA

Input/output package architectures, and methods of using same

INPUT/OUTPUT PACKAGE ARCHITECTURES, AND METHODS OF USING SAME

PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE

METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA

VIA INCLUDING MULTIPLE ELECTRICAL PATHS

Passive within via

Via including multiple electrical paths

Stacked integrated circuit packages and methods of making the packages