Eric J. Dahlen

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 12,079,149
- Issue date Sep 3, 2024
- SK Hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Function as a service (FaaS) system enhancements
- Patent number 11,922,220
- Issue date Mar 5, 2024
- Intel Corporation
- Mohammad R. Haghighat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 11,604,746
- Issue date Mar 14, 2023
- SK hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 11,449,446
- Issue date Sep 20, 2022
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and system for manageability and secure routing...
- Patent number 10,691,839
- Issue date Jun 23, 2020
- Intel Corporation
- Mahesh Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for prioritizing execution of storage commands
- Patent number 10,656,873
- Issue date May 19, 2020
- Intel Corporation
- John W. Carroll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level system main memory
- Patent number 10,365,832
- Issue date Jul 30, 2019
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and system for manageability and secure routing...
- Patent number 9,971,912
- Issue date May 15, 2018
- Intel Corporation
- Mahesh Natu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Two-level system main memory
- Patent number 9,690,493
- Issue date Jun 27, 2017
- Intel Corporation
- Eric J. Dahlen
- G11 - INFORMATION STORAGE
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 9,417,821
- Issue date Aug 16, 2016
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level system main memory
- Patent number 9,087,584
- Issue date Jul 21, 2015
- Intel Corporation
- Eric J. Dahlen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus, and system for manageability and secure routing...
- Patent number 8,930,609
- Issue date Jan 6, 2015
- Intel Corporation
- Mahesh Natu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Enabling idle states for a component associated with an interconnect
- Patent number 8,850,249
- Issue date Sep 30, 2014
- Intel Corporation
- Eric Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level system main memory
- Patent number 8,612,676
- Issue date Dec 17, 2013
- Intel Corporation
- Eric J. Dahlen
- G11 - INFORMATION STORAGE
Information Patent Grant
Enabling idle states for a component associated with an interconnect
- Patent number 7,734,942
- Issue date Jun 8, 2010
- Intel Corporation
- Eric Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for thermal throttling of memory modules
- Patent number 7,318,130
- Issue date Jan 8, 2008
- Intel Corporation
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for command translation and enforcement of ord...
- Patent number 7,194,607
- Issue date Mar 20, 2007
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaved mirrored memory systems
- Patent number 7,130,229
- Issue date Oct 31, 2006
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controllers with interleaved mirrored memory modes
- Patent number 7,076,618
- Issue date Jul 11, 2006
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controllers with interleaved mirrored memory modes
- Patent number 7,017,017
- Issue date Mar 21, 2006
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translation
- Patent number 6,832,274
- Issue date Dec 14, 2004
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing bimodal voltage references for d...
- Patent number 6,769,041
- Issue date Jul 27, 2004
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arrangements for independent queuing/tracking of transaction portio...
- Patent number 6,601,117
- Issue date Jul 29, 2003
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for command translation and enforcement of ord...
- Patent number 6,567,883
- Issue date May 20, 2003
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing bimodal voltage references for d...
- Patent number 6,449,669
- Issue date Sep 10, 2002
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20240378160
- Publication date Nov 14, 2024
- SK hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20230185747
- Publication date Jun 15, 2023
- SK hynix NAND Product Solutions Corp.
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-PACKAGE ACCELERATOR COMPLEX (AC) FOR INTEGRATING ACCELERATOR AND...
- Publication number 20220222194
- Publication date Jul 14, 2022
- Intel Corporation
- Neelam CHANDWANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS
- Publication number 20210263779
- Publication date Aug 26, 2021
- Intel Corporation
- Mohammad R. Haghighat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20200349100
- Publication date Nov 5, 2020
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20190243558
- Publication date Aug 8, 2019
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, Apparatus, and System for Manageability and Secure Routing...
- Publication number 20190138756
- Publication date May 9, 2019
- Intel Corporation
- Mahesh NATU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PRIORITIZING EXECUTION OF STORAGE COMMANDS
- Publication number 20180173461
- Publication date Jun 21, 2018
- John W. Carroll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20180004432
- Publication date Jan 4, 2018
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20160335208
- Publication date Nov 17, 2016
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20160041772
- Publication date Feb 11, 2016
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, Apparatus, and System for Manageability and Secure Routing...
- Publication number 20150096051
- Publication date Apr 2, 2015
- Mahesh NATU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20140351660
- Publication date Nov 27, 2014
- Eric J. DAHLEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20140189212
- Publication date Jul 3, 2014
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20120166891
- Publication date Jun 28, 2012
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for manageability and secure routing...
- Publication number 20120047309
- Publication date Feb 23, 2012
- Mahesh Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enabling Idle States For A Component Associated With An Interconnect
- Publication number 20100205503
- Publication date Aug 12, 2010
- Eric Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLUSHING WRITE BUFFERS
- Publication number 20090113085
- Publication date Apr 30, 2009
- Chris J. Banyai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enabling idle states for a component associated with an interconnect
- Publication number 20080162964
- Publication date Jul 3, 2008
- Eric Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for thermal throttling of memory modules
- Publication number 20050289292
- Publication date Dec 29, 2005
- Warren R. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controllers with interleaved mirrored memory modes
- Publication number 20050262388
- Publication date Nov 24, 2005
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interleaved mirrored memory systems
- Publication number 20040090827
- Publication date May 13, 2004
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controllers with interleaved mirrored memory modes
- Publication number 20040093472
- Publication date May 13, 2004
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Arrangements for independent queuing/tracking of transaction portio...
- Publication number 20030200365
- Publication date Oct 23, 2003
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for command translation and enforcement of ord...
- Publication number 20030189573
- Publication date Oct 9, 2003
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for providing bimodal voltage references for d...
- Publication number 20020108067
- Publication date Aug 8, 2002
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING

Eric J. Dahlen

Person

Patents Grantslast 30 patents

Presentation of direct accessed storage under a logical drive model

Function as a service (FaaS) system enhancements

Presentation of direct accessed storage under a logical drive model

Presentation of direct accessed storage under a logical drive model

Method, apparatus, and system for manageability and secure routing...

Technologies for prioritizing execution of storage commands

Two-level system main memory

Method, apparatus, and system for manageability and secure routing...

Two-level system main memory

Presentation of direct accessed storage under a logical drive model

Two-level system main memory

Method, apparatus, and system for manageability and secure routing...

Enabling idle states for a component associated with an interconnect

Two-level system main memory

Enabling idle states for a component associated with an interconnect

System and method for thermal throttling of memory modules

Method and apparatus for command translation and enforcement of ord...

Interleaved mirrored memory systems

Memory controllers with interleaved mirrored memory modes

Memory controllers with interleaved mirrored memory modes

Address translation

Method and apparatus for providing bimodal voltage references for d...

Arrangements for independent queuing/tracking of transaction portio...

Method and apparatus for command translation and enforcement of ord...

Method and apparatus for providing bimodal voltage references for d...

Patents Applicationslast 30 patents

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

ON-PACKAGE ACCELERATOR COMPLEX (AC) FOR INTEGRATING ACCELERATOR AND...

FUNCTION AS A SERVICE (FAAS) SYSTEM ENHANCEMENTS

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

TWO-LEVEL SYSTEM MAIN MEMORY

Method, Apparatus, and System for Manageability and Secure Routing...

TECHNOLOGIES FOR PRIORITIZING EXECUTION OF STORAGE COMMANDS

TWO-LEVEL SYSTEM MAIN MEMORY

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

TWO-LEVEL SYSTEM MAIN MEMORY

Method, Apparatus, and System for Manageability and Secure Routing...

TWO-LEVEL SYSTEM MAIN MEMORY

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

TWO-LEVEL SYSTEM MAIN MEMORY

Method, apparatus, and system for manageability and secure routing...

Enabling Idle States For A Component Associated With An Interconnect

FLUSHING WRITE BUFFERS

Enabling idle states for a component associated with an interconnect

System and method for thermal throttling of memory modules

Memory controllers with interleaved mirrored memory modes

Interleaved mirrored memory systems

Memory controllers with interleaved mirrored memory modes

Arrangements for independent queuing/tracking of transaction portio...

Method and apparatus for command translation and enforcement of ord...

Method and apparatus for providing bimodal voltage references for d...