Eric J. Stave

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power management for a memory device
- Patent number 12,197,264
- Issue date Jan 14, 2025
- Micron Technology, Inc.
- James S. Rehmeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for memory power management and memory devices and systems...
- Patent number 12,112,830
- Issue date Oct 8, 2024
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and techniques for jitter reduction
- Patent number 12,068,751
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Test devices having parallel impedances to reduce measurement input...
- Patent number 12,051,478
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die termination configuration for a memory device
- Patent number 11,977,751
- Issue date May 7, 2024
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for tuning command/address bus timing and memory devices an...
- Patent number 11,948,661
- Issue date Apr 2, 2024
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus with data-rate-based voltage control mechanism and method...
- Patent number 11,881,245
- Issue date Jan 23, 2024
- Gary L. Howe
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for triggering oscilloscopes and oscilloscopes employing th...
- Patent number 11,867,726
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Daniel B. Stewart
- G01 - MEASURING TESTING
Information Patent Grant
Memory devices, modules and systems having memory devices with vary...
- Patent number 11,789,890
- Issue date Oct 17, 2023
- Thomas H. Kinsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses for characterizing system channels and associated metho...
- Patent number 11,728,001
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Markus H. Geiger
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for on-die memory termination and memory devices and system...
- Patent number 11,586,386
- Issue date Feb 21, 2023
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage adjustment based on pending refresh operations
- Patent number 11,568,913
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Timothy M. Hollis
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for on-die memory termination and memory devices and system...
- Patent number 11,545,199
- Issue date Jan 3, 2023
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for memory power management and memory devices and systems...
- Patent number 11,508,422
- Issue date Nov 22, 2022
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Addressing scheme for a memory system
- Patent number 11,494,323
- Issue date Nov 8, 2022
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus with data-rate-based voltage control mechanism and method...
- Patent number 11,462,254
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Gary L. Howe
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices, modules and systems having memory devices with vary...
- Patent number 11,416,437
- Issue date Aug 16, 2022
- Micron Technology, Inc.
- Thomas H. Kinsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing of read and write operations to reduce interference, and rel...
- Patent number 11,393,513
- Issue date Jul 19, 2022
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with per pin input/output termination and driver impedance c...
- Patent number 11,217,284
- Issue date Jan 4, 2022
- Micron Technology, Inc.
- Eric J. Stave
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Addressing scheme for a memory system
- Patent number 11,080,219
- Issue date Aug 3, 2021
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing continuous time linear equaliza...
- Patent number 11,031,070
- Issue date Jun 8, 2021
- Micron Technology, Inc.
- Todd M. Buerkle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for on-die memory termination and memory devices and system...
- Patent number 11,003,386
- Issue date May 11, 2021
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for on-die memory termination and memory devices and system...
- Patent number 10,950,282
- Issue date Mar 16, 2021
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for on-die memory termination and memory devices and system...
- Patent number 10,424,356
- Issue date Sep 24, 2019
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data pattern generation for I/O training and characterization
- Patent number 9,122,570
- Issue date Sep 1, 2015
- Nanya Technology Corp.
- Timothy M. Hollis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real time testing using on die termination (ODT) circuit
- Patent number 7,664,999
- Issue date Feb 16, 2010
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Real time testing using on die termination (ODT) circuit
- Patent number 7,574,634
- Issue date Aug 11, 2009
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power chip select (CS) latency option
- Patent number 7,274,606
- Issue date Sep 25, 2007
- Micron Technology, Inc.
- Eric Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power chip select (CS) latency option
- Patent number 7,167,401
- Issue date Jan 23, 2007
- Micron Technology, Inc.
- Eric Stave
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor buffer circuit with a transition delay circuit
- Patent number 6,788,126
- Issue date Sep 7, 2004
- Micron Technology, Inc.
- Eric J. Stave
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ON DIE CLOCK JITTER INJECTION FOR ELECTROMAGNETIC INTERFERENCE REDU...
- Publication number 20240314990
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
OPTICAL SIGNALING FOR STACKED MEMORY DEVICE ARCHITECTURES
- Publication number 20240268131
- Publication date Aug 8, 2024
- Micron Technology, Inc.
- Timothy M. Hollis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR TUNING COMMAND/ADDRESS BUS TIMING AND MEMORY DEVICES AN...
- Publication number 20240249758
- Publication date Jul 25, 2024
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...
- Publication number 20240221813
- Publication date Jul 4, 2024
- Lodestar Licensing Group LLC
- Gary L. Howe
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARY...
- Publication number 20240111707
- Publication date Apr 4, 2024
- Lodestar Licensing Group LLC
- Thomas H. Kinsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND TECHNIQUES FOR JITTER REDUCTION
- Publication number 20240007092
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDI...
- Publication number 20230386596
- Publication date Nov 30, 2023
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
ON-DIE TERMINATION CONFIGURATION FOR A MEMORY DEVICE
- Publication number 20230117882
- Publication date Apr 20, 2023
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS
- Publication number 20230120654
- Publication date Apr 20, 2023
- Micron Technology, Inc.
- Timothy M. Hollis
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS...
- Publication number 20230084286
- Publication date Mar 16, 2023
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...
- Publication number 20230021201
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Gary L. Howe
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARY...
- Publication number 20220335000
- Publication date Oct 20, 2022
- Micron Technology, Inc.
- Thomas H. Kinsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST DEVICES HAVING PARALLEL IMPEDANCES TO REDUCE MEASUREMENT INPUT...
- Publication number 20220199193
- Publication date Jun 23, 2022
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
TIMING OF READ AND WRITE OPERATIONS TO REDUCE INTERFERENCE, AND REL...
- Publication number 20220172755
- Publication date Jun 2, 2022
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES FOR CHARACTERIZING SYSTEM CHANNELS AND ASSOCIATED METHO...
- Publication number 20220157396
- Publication date May 19, 2022
- Micron Technology, Inc.
- Markus H. Geiger
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGEMENT FOR A MEMORY DEVICE
- Publication number 20220147131
- Publication date May 12, 2022
- Micron Technology, Inc.
- James S. Rehmeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...
- Publication number 20220148638
- Publication date May 12, 2022
- Micron Technology, Inc.
- Gary L. Howe
- G11 - INFORMATION STORAGE
Information Patent Application
ADDRESSING SCHEME FOR A MEMORY SYSTEM
- Publication number 20220058145
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR TUNING COMMAND/ADDRESS BUS TIMING AND MEMORY DEVICES AN...
- Publication number 20210383849
- Publication date Dec 9, 2021
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH PER PIN INPUT/OUTPUT TERMINATION AND DRIVER IMPEDANCE C...
- Publication number 20210312958
- Publication date Oct 7, 2021
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...
- Publication number 20210263685
- Publication date Aug 26, 2021
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS
- Publication number 20210241810
- Publication date Aug 5, 2021
- Micron Technology, Inc.
- Timothy M. Hollis
- G11 - INFORMATION STORAGE
Information Patent Application
ADDRESSING SCHEME FOR A MEMORY SYSTEM
- Publication number 20210216479
- Publication date Jul 15, 2021
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...
- Publication number 20210201970
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR TRIGGERING OSCILLOSCOPES AND OSCILLOSCOPES EMPLOYING TH...
- Publication number 20210072287
- Publication date Mar 11, 2021
- Micron Technology, Inc.
- Daniel B. Stewart
- G01 - MEASURING TESTING
Information Patent Application
METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS...
- Publication number 20210035617
- Publication date Feb 4, 2021
- Micron Technology, Inc.
- Eric J. Stave
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARY...
- Publication number 20200201807
- Publication date Jun 25, 2020
- Micron Technology, Inc.
- Thomas H. Kinsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...
- Publication number 20190371379
- Publication date Dec 5, 2019
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...
- Publication number 20190156871
- Publication date May 23, 2019
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...
- Publication number 20190155544
- Publication date May 23, 2019
- Micron Technology, Inc.
- Eric J. Stave
- G06 - COMPUTING CALCULATING COUNTING

Eric J. Stave

Person

Patents Grantslast 30 patents

Power management for a memory device

Methods for memory power management and memory devices and systems...

Systems and techniques for jitter reduction

Test devices having parallel impedances to reduce measurement input...

On-die termination configuration for a memory device

Methods for tuning command/address bus timing and memory devices an...

Apparatus with data-rate-based voltage control mechanism and method...

Methods for triggering oscilloscopes and oscilloscopes employing th...

Memory devices, modules and systems having memory devices with vary...

Apparatuses for characterizing system channels and associated metho...

Methods for on-die memory termination and memory devices and system...

Voltage adjustment based on pending refresh operations

Methods for on-die memory termination and memory devices and system...

Methods for memory power management and memory devices and systems...

Addressing scheme for a memory system

Apparatus with data-rate-based voltage control mechanism and method...

Memory devices, modules and systems having memory devices with vary...

Timing of read and write operations to reduce interference, and rel...

Memory with per pin input/output termination and driver impedance c...

Addressing scheme for a memory system

Apparatus and method for performing continuous time linear equaliza...

Methods for on-die memory termination and memory devices and system...

Methods for on-die memory termination and memory devices and system...

Methods for on-die memory termination and memory devices and system...

Data pattern generation for I/O training and characterization

Real time testing using on die termination (ODT) circuit

Real time testing using on die termination (ODT) circuit

Low power chip select (CS) latency option

Low power chip select (CS) latency option

Semiconductor buffer circuit with a transition delay circuit

Patents Applicationslast 30 patents

ON DIE CLOCK JITTER INJECTION FOR ELECTROMAGNETIC INTERFERENCE REDU...

OPTICAL SIGNALING FOR STACKED MEMORY DEVICE ARCHITECTURES

METHODS FOR TUNING COMMAND/ADDRESS BUS TIMING AND MEMORY DEVICES AN...

APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...

MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARY...

SYSTEMS AND TECHNIQUES FOR JITTER REDUCTION

INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDI...

ON-DIE TERMINATION CONFIGURATION FOR A MEMORY DEVICE

VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS

METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS...

APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...

MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARY...

TEST DEVICES HAVING PARALLEL IMPEDANCES TO REDUCE MEASUREMENT INPUT...

TIMING OF READ AND WRITE OPERATIONS TO REDUCE INTERFERENCE, AND REL...

APPARATUSES FOR CHARACTERIZING SYSTEM CHANNELS AND ASSOCIATED METHO...

POWER MANAGEMENT FOR A MEMORY DEVICE

APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...

ADDRESSING SCHEME FOR A MEMORY SYSTEM

METHODS FOR TUNING COMMAND/ADDRESS BUS TIMING AND MEMORY DEVICES AN...

MEMORY WITH PER PIN INPUT/OUTPUT TERMINATION AND DRIVER IMPEDANCE C...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...

VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS

ADDRESSING SCHEME FOR A MEMORY SYSTEM

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...

METHODS FOR TRIGGERING OSCILLOSCOPES AND OSCILLOSCOPES EMPLOYING TH...

METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS...

MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARY...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...

METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEM...