Eric M. Rentschler

Person

Steamboat Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Distributed on-chip debug triggering with allocated bus lines
- Patent number 9,442,815
- Issue date Sep 13, 2016
- Advanced Micro Devices, Inc.
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug apparatus and methods for dynamically switching power domains
- Patent number 9,329,963
- Issue date May 3, 2016
- Advanced Micro Devices, Inc.
- Shantanu K. Sarangi
- G01 - MEASURING TESTING
Information Patent Grant
Debug apparatus and methods for dynamically switching power domains
- Patent number 9,262,293
- Issue date Feb 16, 2016
- Advanced Micro Devices, Inc.
- Shantanu K. Sarangi
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for on-chip debugging
- Patent number 9,129,061
- Issue date Sep 8, 2015
- Advanced Micro Devices, Inc.
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug state machines and methods of their operation
- Patent number 9,037,911
- Issue date May 19, 2015
- Advanced Micro Devices, Inc.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple clock domain debug capability
- Patent number 8,959,398
- Issue date Feb 17, 2015
- Advanced Micro Devices, Inc.
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Correlating traces in a computing system
- Patent number 8,935,574
- Issue date Jan 13, 2015
- Advanced Micro Devices, Inc.
- Ryan D. Bedwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple clock domain tracing
- Patent number 8,832,500
- Issue date Sep 9, 2014
- Advanced Micro Devices, Inc.
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug state machine cross triggering
- Patent number 8,683,265
- Issue date Mar 25, 2014
- Advanced Micro Devices, Inc.
- Eric M. Rentschler
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuitry for debugging a power-gated circuit
- Patent number 8,595,563
- Issue date Nov 26, 2013
- Advanced Micro Devices, Inc.
- Benjamin Tsien
- G01 - MEASURING TESTING
Information Patent Grant
Debug state machine and processor including the same
- Patent number 8,566,645
- Issue date Oct 22, 2013
- Advanced Micro Devices, Inc.
- Eric Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for implementing bus locking with a mixed architecture
- Patent number 6,381,663
- Issue date Apr 30, 2002
- Hewlett-Packard Company
- John A. Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherency protocol for computer cache
- Patent number 6,360,301
- Issue date Mar 19, 2002
- Hewlett-Packard Company
- Blaine D Gaither
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for dynamically allocating data among geometry ac...
- Patent number 5,940,086
- Issue date Aug 17, 1999
- Hewlett-Packard Company
- Eric Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching and coherency control of multiple geometry accelerators in...
- Patent number 5,920,326
- Issue date Jul 6, 1999
- Hewlett-Packard Company
- Eric Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for finding m modulo n
- Patent number 5,793,660
- Issue date Aug 11, 1998
- Hewlett-Packard Company
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DEBUG APPARATUS AND METHODS FOR DYNAMICALLY SWITCHING POWER DOMAINS
- Publication number 20150082093
- Publication date Mar 19, 2015
- Advanced Micro Devices, Inc.
- Shantanu K. Sarangi
- G01 - MEASURING TESTING
Information Patent Application
DEBUG APPARATUS AND METHODS FOR DYNAMICALLY SWITCHING POWER DOMAINS
- Publication number 20150082092
- Publication date Mar 19, 2015
- Advanced Micro Devices, Inc.
- Shantanu K. Sarangi
- G01 - MEASURING TESTING
Information Patent Application
DISTRIBUTED ON-CHIP DEBUG TRIGGERING
- Publication number 20140122929
- Publication date May 1, 2014
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE CLOCK DOMAIN DEBUG CAPABILITY
- Publication number 20140053027
- Publication date Feb 20, 2014
- Advanced Micro Devices, Inc.
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUGGING MULTIPLE EXCLUSIVE SEQUENCES USING DSM CONTEXT SWITCHES
- Publication number 20140053036
- Publication date Feb 20, 2014
- Scott P. Nixon
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE CLOCK DOMAIN TRACING
- Publication number 20140047262
- Publication date Feb 13, 2014
- Advanced Micro Devices, Inc.
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ON-CHIP DEBUGGING
- Publication number 20140032801
- Publication date Jan 30, 2014
- Advanced Micro Devices and ATI Technologies ULC
- Scott P. Nixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORRELATING TRACES IN A COMPUTING SYSTEM
- Publication number 20130159780
- Publication date Jun 20, 2013
- Ryan D. Bedwell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT
- Publication number 20130024829
- Publication date Jan 24, 2013
- Advanced Micro Devices, Inc.
- Benjamin Tsien
- G01 - MEASURING TESTING
Information Patent Application
DEBUG STATE MACHINE CROSS TRIGGERING
- Publication number 20120150474
- Publication date Jun 14, 2012
- Advanced Micro Devices, Inc.
- Eric M. Rentschler
- G01 - MEASURING TESTING
Information Patent Application
DEBUG STATE MACHINE CROSS TRIGGERING
- Publication number 20120146658
- Publication date Jun 14, 2012
- Advanced Micro Devices, Inc.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG STATE MACHINES AND METHODS OF THEIR OPERATION
- Publication number 20120151263
- Publication date Jun 14, 2012
- Advanced Micro Devices, Inc.
- Eric M. RENTSCHLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG STATE MACHINE AND PROCESSOR INCLUDING THE SAME
- Publication number 20120144240
- Publication date Jun 7, 2012
- Advanced Micro Devices, Inc.
- Eric Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR IMPLEMENTING BUS LOCKING WITH A MIXED ARCHITECTURE
- Publication number 20020038398
- Publication date Mar 28, 2002
- JOHN A. MORRISON
- G06 - COMPUTING CALCULATING COUNTING

Eric M. Rentschler

Person

Patents Grantslast 30 patents

Distributed on-chip debug triggering with allocated bus lines

Debug apparatus and methods for dynamically switching power domains

Debug apparatus and methods for dynamically switching power domains

Method and apparatus for on-chip debugging

Debug state machines and methods of their operation

Multiple clock domain debug capability

Correlating traces in a computing system

Multiple clock domain tracing

Debug state machine cross triggering

Method and circuitry for debugging a power-gated circuit

Debug state machine and processor including the same

Mechanism for implementing bus locking with a mixed architecture

Coherency protocol for computer cache

System and method for dynamically allocating data among geometry ac...

Caching and coherency control of multiple geometry accelerators in...

Circuit for finding m modulo n

Patents Applicationslast 30 patents

DEBUG APPARATUS AND METHODS FOR DYNAMICALLY SWITCHING POWER DOMAINS

DEBUG APPARATUS AND METHODS FOR DYNAMICALLY SWITCHING POWER DOMAINS

DISTRIBUTED ON-CHIP DEBUG TRIGGERING

MULTIPLE CLOCK DOMAIN DEBUG CAPABILITY

DEBUGGING MULTIPLE EXCLUSIVE SEQUENCES USING DSM CONTEXT SWITCHES

MULTIPLE CLOCK DOMAIN TRACING

METHOD AND APPARATUS FOR ON-CHIP DEBUGGING

CORRELATING TRACES IN A COMPUTING SYSTEM

METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT

DEBUG STATE MACHINE CROSS TRIGGERING

DEBUG STATE MACHINE CROSS TRIGGERING

DEBUG STATE MACHINES AND METHODS OF THEIR OPERATION

DEBUG STATE MACHINE AND PROCESSOR INCLUDING THE SAME

MECHANISM FOR IMPLEMENTING BUS LOCKING WITH A MIXED ARCHITECTURE