Eric Neyret

Person

Sassenage, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Progressive trimming method
- Patent number 8,679,944
- Issue date Mar 25, 2014
- Soitec
- Marcel Broekaart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Treatment for bonding interface stabilization
- Patent number 8,461,018
- Issue date Jun 11, 2013
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Finishing method for a silicon on insulator substrate
- Patent number 8,389,412
- Issue date Mar 5, 2013
- Soitec
- Walter Schwarzenbach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for the transfer of a thin layer formed in a substrate with...
- Patent number 8,273,636
- Issue date Sep 25, 2012
- Soitec
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Treatment for bonding interface stabilization
- Patent number 8,216,916
- Issue date Jul 10, 2012
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor on insulator substrate with...
- Patent number 7,947,571
- Issue date May 24, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Luciana Capello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a substrate of the silicon-on-insulator typ...
- Patent number 7,939,427
- Issue date May 10, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing the surface roughness of a semiconductor wafer
- Patent number 7,883,628
- Issue date Feb 8, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Treatment for bonding interface stabilization
- Patent number 7,863,158
- Issue date Jan 4, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing the surface roughness of a semiconductor wafer
- Patent number 7,749,910
- Issue date Jul 6, 2010
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a substrate of the silicon-on-insulator typ...
- Patent number 7,666,758
- Issue date Feb 23, 2010
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Finishing process for the manufacture of a semiconductor structure
- Patent number 7,514,341
- Issue date Apr 7, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of configuring a process to obtain a thin layer with a low d...
- Patent number 7,485,545
- Issue date Feb 3, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- Nadia Ben Mohamed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for manufacturing compound-material wafers and for recyclin...
- Patent number 7,405,136
- Issue date Jul 29, 2008
- S.O.I. Tec Silicon on Insulator Technologies
- Daniel Delprat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for transfer of a thin layer formed in a substrate with vac...
- Patent number 7,285,471
- Issue date Oct 23, 2007
- S.O.I. Tec Silicon on Insulator Technologies
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preventive treatment method for a multilayer semiconductor wafer
- Patent number 7,190,029
- Issue date Mar 13, 2007
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for minimizing slip line faults on a semiconductor wafer sur...
- Patent number 7,138,344
- Issue date Nov 21, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a high quality useful layer on a substrate uti...
- Patent number 7,081,399
- Issue date Jul 25, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heat treatment for edges of multilayer semiconductor wafers
- Patent number 7,049,250
- Issue date May 23, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for limiting slip lines in a semiconductor substrate
- Patent number 7,001,832
- Issue date Feb 21, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing free surface roughness of a semiconductor wafer
- Patent number 6,962,858
- Issue date Nov 8, 2005
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preventive treatment method for a multilayer semiconductor wafer
- Patent number 6,939,783
- Issue date Sep 6, 2005
- S.O.I.Tec Silicon on Insulator Technologies, S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for preparing a semiconductor wafer surface
- Patent number 6,903,032
- Issue date Jun 7, 2005
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heat treatment for edges of multilayer semiconductor wafers
- Patent number 6,853,802
- Issue date Feb 8, 2005
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR REDUCING SURFACE ROUGHNESS WHILE PRODUCING A HIGH QUALIT...
- Publication number 20150221545
- Publication date Aug 6, 2015
- SOITEC
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINISHING METHOD FOR A SILICON ON INSULATOR SUBSTRATE
- Publication number 20120021613
- Publication date Jan 26, 2012
- Walter Schwarzenbach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TREATMENT FOR BONDING INTERFACE STABILIZATION
- Publication number 20110233720
- Publication date Sep 29, 2011
- S. O. I. Tec Silicon on Insulator Technologies
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIXED TRIMMING METHOD
- Publication number 20110117691
- Publication date May 19, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Marcel Broekaart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRESSIVE TRIMMING METHOD
- Publication number 20110097874
- Publication date Apr 28, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Marcel Broekaart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for the transfer of a thin layer formed in a substrate with...
- Publication number 20110097871
- Publication date Apr 28, 2011
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH...
- Publication number 20100052092
- Publication date Mar 4, 2010
- Luciana Capello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FABRICATING A SUBSTRATE OF THE SILICON-ON-INSULATOR TYP...
- Publication number 20090035920
- Publication date Feb 5, 2009
- Eric NEYRET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FABRICATING A SUBSTRATE OF THE SILICON-ON-INSULATOR TYP...
- Publication number 20080188060
- Publication date Aug 7, 2008
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Treatment for bonding interface stabilization
- Publication number 20080014718
- Publication date Jan 17, 2008
- S.O.I TEC Silicon on Insulator Technologies S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Treatment for bonding interface stabilization
- Publication number 20080014713
- Publication date Jan 17, 2008
- S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for manufacturing compound-material wafers and for recyclin...
- Publication number 20070216042
- Publication date Sep 20, 2007
- Daniel Delprat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for simplification of a finishing sequence and structure ob...
- Publication number 20070148910
- Publication date Jun 28, 2007
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for producing a high quality useful layer on a substrate
- Publication number 20060223283
- Publication date Oct 5, 2006
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for transfer of a thin layer formed in a substrate with vac...
- Publication number 20060172508
- Publication date Aug 3, 2006
- Christophe Maleville
- C30 - CRYSTAL GROWTH
Information Patent Application
Method of configuring a process to obtain a thin layer with a low d...
- Publication number 20060141755
- Publication date Jun 29, 2006
- Nadia Ben Mohamed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of reducing the surface roughness of a semiconductor wafer
- Publication number 20060035445
- Publication date Feb 16, 2006
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of reducing the surface roughness of a semiconductor wafer
- Publication number 20060024908
- Publication date Feb 2, 2006
- S.I.O.TEC Silicon on Insulator Technologes S.A.
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Preventive treatment method for a multilayer semiconductor wafer
- Publication number 20050230754
- Publication date Oct 20, 2005
- S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A., a French corporate
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR LIMITING SLIP LINES IN A SEMICONDUCTOR SUBSTRATE
- Publication number 20050202658
- Publication date Sep 15, 2005
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Heat treatment for edges of multilayer semiconductor wafers
- Publication number 20050094990
- Publication date May 5, 2005
- S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A., a French corporate
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for producing a high quality useful layer on a substrate
- Publication number 20050026426
- Publication date Feb 3, 2005
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Preventive treatment method for a multilayer semiconductor wafer
- Publication number 20040197963
- Publication date Oct 7, 2004
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing free surface roughness of a semiconductor wafer
- Publication number 20040171257
- Publication date Sep 2, 2004
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for preparing a semiconductor wafer surface
- Publication number 20040161948
- Publication date Aug 19, 2004
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Heat treatment for edges of multilayer semiconductor wafers
- Publication number 20040151483
- Publication date Aug 5, 2004
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for minimizing slip line faults on a semiconductor wafer sur...
- Publication number 20040106303
- Publication date Jun 3, 2004
- Eric Neyret
- H01 - BASIC ELECTRIC ELEMENTS

Eric Neyret

Person

Patents Grantslast 30 patents

Progressive trimming method

Treatment for bonding interface stabilization

Finishing method for a silicon on insulator substrate

Process for the transfer of a thin layer formed in a substrate with...

Treatment for bonding interface stabilization

Method for fabricating a semiconductor on insulator substrate with...

Process for fabricating a substrate of the silicon-on-insulator typ...

Method of reducing the surface roughness of a semiconductor wafer

Treatment for bonding interface stabilization

Method of reducing the surface roughness of a semiconductor wafer

Process for fabricating a substrate of the silicon-on-insulator typ...

Finishing process for the manufacture of a semiconductor structure

Method of configuring a process to obtain a thin layer with a low d...

Methods for manufacturing compound-material wafers and for recyclin...

Process for transfer of a thin layer formed in a substrate with vac...

Preventive treatment method for a multilayer semiconductor wafer

Method for minimizing slip line faults on a semiconductor wafer sur...

Method for producing a high quality useful layer on a substrate uti...

Heat treatment for edges of multilayer semiconductor wafers

Method for limiting slip lines in a semiconductor substrate

Method for reducing free surface roughness of a semiconductor wafer

Preventive treatment method for a multilayer semiconductor wafer

Method for preparing a semiconductor wafer surface

Heat treatment for edges of multilayer semiconductor wafers

Patents Applicationslast 30 patents

METHOD FOR REDUCING SURFACE ROUGHNESS WHILE PRODUCING A HIGH QUALIT...

FINISHING METHOD FOR A SILICON ON INSULATOR SUBSTRATE

TREATMENT FOR BONDING INTERFACE STABILIZATION

MIXED TRIMMING METHOD

PROGRESSIVE TRIMMING METHOD

Process for the transfer of a thin layer formed in a substrate with...

METHOD FOR FABRICATING A SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH...

PROCESS FOR FABRICATING A SUBSTRATE OF THE SILICON-ON-INSULATOR TYP...

PROCESS FOR FABRICATING A SUBSTRATE OF THE SILICON-ON-INSULATOR TYP...

Treatment for bonding interface stabilization

Treatment for bonding interface stabilization

Methods for manufacturing compound-material wafers and for recyclin...

Process for simplification of a finishing sequence and structure ob...

Method for producing a high quality useful layer on a substrate

Process for transfer of a thin layer formed in a substrate with vac...

Method of configuring a process to obtain a thin layer with a low d...

Method of reducing the surface roughness of a semiconductor wafer

Method of reducing the surface roughness of a semiconductor wafer

Preventive treatment method for a multilayer semiconductor wafer

METHOD FOR LIMITING SLIP LINES IN A SEMICONDUCTOR SUBSTRATE

Heat treatment for edges of multilayer semiconductor wafers

Method for producing a high quality useful layer on a substrate

Preventive treatment method for a multilayer semiconductor wafer

Method for reducing free surface roughness of a semiconductor wafer

Method for preparing a semiconductor wafer surface

Heat treatment for edges of multilayer semiconductor wafers

Method for minimizing slip line faults on a semiconductor wafer sur...