Eric Rentschler

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for aggregation and streaming of monitoring data
- Patent number 9,686,536
- Issue date Jun 20, 2017
- Advanced Micro Devices, Inc.
- Eric Rentschler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronizing link delay measurement over serial links
- Patent number 7,533,285
- Issue date May 12, 2009
- Hewlett-Packard Development Company, L.P.
- Samuel D. Naffziger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mirrored computer memory on split bus
- Patent number 7,506,130
- Issue date Mar 17, 2009
- Hewlett-Packard Development Company, L.P.
- Darel N. Emmot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with a scalable high-bandwidth architecture
- Patent number 7,426,596
- Issue date Sep 16, 2008
- Hewlett-Packard Development Company, L.P.
- Darel Emmot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repeatability over communication links
- Patent number 7,289,587
- Issue date Oct 30, 2007
- Hewlett-Packard Development Company, L.P.
- Eric M. Rentschler
- G01 - MEASURING TESTING
Information Patent Grant
Memory controller driver circuitry having a multiplexing stage to p...
- Patent number 7,103,790
- Issue date Sep 5, 2006
- Hewlett-Packard Development Company, L.P.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and controller for same
- Patent number 7,103,826
- Issue date Sep 5, 2006
- Hewlett-Packard Development Company, L.P.
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller having receiver circuitry capable of alternately...
- Patent number 7,103,793
- Issue date Sep 5, 2006
- Hewlett-Packard Development Company, L.P.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAID memory system
- Patent number 7,099,994
- Issue date Aug 29, 2006
- Hewlett-Packard Development Company, L.P.
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller to communicate with memory devices that are assoc...
- Patent number 6,990,562
- Issue date Jan 24, 2006
- Hewlett-Packard Development Company, L.P.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data signal reception latch control using clock aligned relative to...
- Patent number 6,930,932
- Issue date Aug 16, 2005
- Hewlett-Packard Development Company, L.P.
- Eric McCutcheon Rentschler
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller receiver circuitry with tri-state noise immunity
- Patent number 6,889,335
- Issue date May 3, 2005
- Hewlett-Packard Development Company, L.P.
- Jeffrey G. Hargis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Terminating pathway for a clock signal
- Patent number 6,788,135
- Issue date Sep 7, 2004
- Hewlett-Packard Development Company, L.P.
- Lisa Ann Yunker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with 1X/MX write capability
- Patent number 6,678,811
- Issue date Jan 13, 2004
- Hewlett-Packard Development Company, L.P.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with 1×/M× read capability
- Patent number 6,633,965
- Issue date Oct 14, 2003
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with support for memory modules comprised of non-...
- Patent number 6,625,702
- Issue date Sep 23, 2003
- Hewlett-Packard Development Company, L.P.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching and coherency control of multiple geometry accelerators in...
- Patent number 5,969,726
- Issue date Oct 19, 1999
- Hewlett-Packard Co.
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer graphics system utilizing parallel processing for enhanced...
- Patent number 5,821,950
- Issue date Oct 13, 1998
- Hewlett-Packard Company
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data bus protocol for computer graphics system
- Patent number 5,671,373
- Issue date Sep 23, 1997
- Hewlett-Packard Company
- Bryan G. Prouty
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS

Patents Applicationslast 30 patents

Information Patent Application
Repeatability over communication links
- Publication number 20050240698
- Publication date Oct 27, 2005
- Eric M. Rentschler
- G01 - MEASURING TESTING
Information Patent Application
Synchronizing link delay measurement over serial links
- Publication number 20050238127
- Publication date Oct 27, 2005
- Samuel D. Naffziger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RAID memory system
- Publication number 20050071554
- Publication date Mar 31, 2005
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data signal reception latch control using clock aligned relative to...
- Publication number 20050047222
- Publication date Mar 3, 2005
- Eric McCutcheon Rentschler
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit with a scalable high-bandwidth architecture
- Publication number 20050027891
- Publication date Feb 3, 2005
- Darel Emmot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system and controller for same
- Publication number 20050028069
- Publication date Feb 3, 2005
- Larry Thayer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller to communicate with memory devices that are assoc...
- Publication number 20040158688
- Publication date Aug 12, 2004
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with 1X/MX read capability
- Publication number 20040133757
- Publication date Jul 8, 2004
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with 1x/Mx write capability
- Publication number 20040088512
- Publication date May 6, 2004
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mirrored computer memory on single bus
- Publication number 20030221058
- Publication date Nov 27, 2003
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mirrored computer memory on split bus
- Publication number 20030221059
- Publication date Nov 27, 2003
- Darel N. Emmot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller receiver circuitry with tri-state noise immunity
- Publication number 20020172079
- Publication date Nov 21, 2002
- Jeffrey G. Hargis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with support for memory modules comprised of non-...
- Publication number 20020147898
- Publication date Oct 10, 2002
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with 1X/MX write capability
- Publication number 20020147896
- Publication date Oct 10, 2002
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with 1X/MX read capability
- Publication number 20020147892
- Publication date Oct 10, 2002
- Eric M. Rentschler
- G06 - COMPUTING CALCULATING COUNTING

Eric Rentschler

Person

Patents Grantslast 30 patents

Method and apparatus for aggregation and streaming of monitoring data

Synchronizing link delay measurement over serial links

Mirrored computer memory on split bus

Integrated circuit with a scalable high-bandwidth architecture

Repeatability over communication links

Memory controller driver circuitry having a multiplexing stage to p...

Memory system and controller for same

Memory controller having receiver circuitry capable of alternately...

RAID memory system

Memory controller to communicate with memory devices that are assoc...

Data signal reception latch control using clock aligned relative to...

Memory controller receiver circuitry with tri-state noise immunity

Terminating pathway for a clock signal

Memory controller with 1X/MX write capability

Memory controller with 1&#x000D7;/M&#x000D7; read capability

Memory controller with support for memory modules comprised of non-...

Caching and coherency control of multiple geometry accelerators in...

Computer graphics system utilizing parallel processing for enhanced...

Data bus protocol for computer graphics system

Patents Applicationslast 30 patents

Repeatability over communication links

Synchronizing link delay measurement over serial links

RAID memory system

Data signal reception latch control using clock aligned relative to...

Integrated circuit with a scalable high-bandwidth architecture

Memory system and controller for same

Memory controller to communicate with memory devices that are assoc...

Memory controller with 1X/MX read capability

Memory controller with 1x/Mx write capability

Mirrored computer memory on single bus

Mirrored computer memory on split bus

Memory controller receiver circuitry with tri-state noise immunity

Memory controller with support for memory modules comprised of non-...

Memory controller with 1X/MX write capability

Memory controller with 1X/MX read capability

Memory controller with 1×/M× read capability