Eric Wayne MAHURIN

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hybrid convolution operation
- Patent number 12,093,800
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraining function approximation hardware integrated with fixed-...
- Patent number 11,669,747
- Issue date Jun 6, 2023
- QUALCOMM Incorporated
- Rexford Alan Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access management
- Patent number 11,669,273
- Issue date Jun 6, 2023
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting a proxy read instruction in an instruction pipeline in a...
- Patent number 11,609,764
- Issue date Mar 21, 2023
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power control based on performance modification through pulse modul...
- Patent number 11,586,272
- Issue date Feb 21, 2023
- QUALCOMM Incorporated
- Vijay Kiran Kalyanam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus, and method for a transient load instruction with...
- Patent number 11,561,792
- Issue date Jan 24, 2023
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of loading and replication of sub-vector values
- Patent number 11,372,804
- Issue date Jun 28, 2022
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-thread power limiting via shared limit
- Patent number 11,287,872
- Issue date Mar 29, 2022
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G01 - MEASURING TESTING
Information Patent Grant
Proactive clock gating system to mitigate supply voltage droops
- Patent number 10,860,051
- Issue date Dec 8, 2020
- QUALCOMM Incorporated
- Vijay Kiran Kalyanam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor to perform a bit range isolation instruction
- Patent number 10,656,947
- Issue date May 19, 2020
- Intel Corporation
- Maxim Loktyukhin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for online functional testing for error-correctin...
- Patent number 10,625,752
- Issue date Apr 21, 2020
- QUALCOMM Incorporated
- Mohammad Reza Kakoee
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Processor to perform a bit range isolation instruction
- Patent number 10,579,379
- Issue date Mar 3, 2020
- Intel Corporation
- Maxim Loktyukhin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip (SoC) to perform a bit range isolation instruction
- Patent number 10,579,380
- Issue date Mar 3, 2020
- Intel Corporation
- Maxim Loktyukhin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed-width SIMD operations using even/odd register pairs for wide...
- Patent number 10,489,155
- Issue date Nov 26, 2019
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction-based synchronization of operations including at least...
- Patent number 10,474,461
- Issue date Nov 12, 2019
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sliding window operation
- Patent number 10,459,731
- Issue date Oct 29, 2019
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SIMD instructions for multi-stage cube networks
- Patent number 10,459,723
- Issue date Oct 29, 2019
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hand held device to perform a bit range isolation instruction
- Patent number 10,372,455
- Issue date Aug 6, 2019
- Intel Corporation
- Maxim Loktyukhin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of floating point multiply operation processing
- Patent number 10,346,133
- Issue date Jul 9, 2019
- QUALCOMM Incorporated
- Albert Danysh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage at contiguous memory addresses
- Patent number 10,162,752
- Issue date Dec 25, 2018
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling voltage deviations in processing systems
- Patent number 10,152,101
- Issue date Dec 11, 2018
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Coprocessor for out-of-order loads
- Patent number 9,678,758
- Issue date Jun 13, 2017
- QUALCOMM Incorporated
- Lucian Codrescu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional unit for vector leading zeroes, vector trailing zeroes,...
- Patent number 9,092,213
- Issue date Jul 28, 2015
- Intel Corporation
- Jeff Wiedemeier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption and resource utilization during miss loo...
- Patent number 9,009,449
- Issue date Apr 14, 2015
- Oracle International Corporation
- Yuan C. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit range isolation instructions, methods, and apparatus
- Patent number 9,003,170
- Issue date Apr 7, 2015
- Intel Corporation
- Maxim Loktyukhin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching load data in lookahead mode and invalidating architectu...
- Patent number 8,918,626
- Issue date Dec 23, 2014
- Oracle International Corporation
- Yuan C. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplexing using product-of-sums and sum-of-products
- Patent number 7,821,298
- Issue date Oct 26, 2010
- Eric Mahurin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit design with cell-based macros
- Patent number 7,401,310
- Issue date Jul 15, 2008
- Advanced Micro Devices, Inc.
- Robert C. Thaden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for parity tree structure
- Patent number 7,242,219
- Issue date Jul 10, 2007
- Advanced Micro Devices, Inc.
- Eric W. Mahurin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Instruction decode unit producing instruction operand information i...
- Patent number 6,539,470
- Issue date Mar 25, 2003
- Advanced Micro Devices, Inc.
- Eric W. Mahurin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SINGLE INSTRUCTION MULTIPLE DATA (SIMD) SPARSE DECOMPRESSION WITH V...
- Publication number 20240118902
- Publication date Apr 11, 2024
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATED LOW BIT-WIDTH QUANTIZATION USING BIT SHIFTED NEURAL NETWO...
- Publication number 20230306233
- Publication date Sep 28, 2023
- QUALCOMM Incorporated
- Marinus Willem VAN BAALEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSERTING A PROXY READ INSTRUCTION IN AN INSTRUCTION PIPELINE IN A...
- Publication number 20220365780
- Publication date Nov 17, 2022
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Artificial Intelligence Processor Architecture For Dynamic Scaling...
- Publication number 20220309314
- Publication date Sep 29, 2022
- QUALCOMM Incorporated
- Hee Jun PARK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED RESULT MATRIX
- Publication number 20220035891
- Publication date Feb 3, 2022
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-THREAD POWER LIMITING VIA SHARED LIMIT
- Publication number 20210240251
- Publication date Aug 5, 2021
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS MANAGEMENT
- Publication number 20210240394
- Publication date Aug 5, 2021
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID CONVOLUTION OPERATION
- Publication number 20210241070
- Publication date Aug 5, 2021
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER CONTROL BASED ON PERFORMANCE MODIFICATION THROUGH PULSE MODUL...
- Publication number 20210096635
- Publication date Apr 1, 2021
- QUALCOMM Incorporated
- Vijay Kiran KALYANAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRAINING FUNCTION APPROXIMATION HARDWARE INTEGRATED WITH FIXED-...
- Publication number 20200134475
- Publication date Apr 30, 2020
- QUALCOMM Incorporated
- Rexford Alan HILL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROACTIVE CLOCK GATING SYSTEM TO MITIGATE SUPPLY VOLTAGE DROOPS
- Publication number 20200081479
- Publication date Mar 12, 2020
- QUALCOMM Incorporated
- Vijay Kiran KALYANAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF LOADING AND REPLICATION OF SUB-VECTOR VALUES
- Publication number 20190354508
- Publication date Nov 21, 2019
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF FLOATING POINT MULTIPLY OPERATION PROCESSING
- Publication number 20190196785
- Publication date Jun 27, 2019
- QUALCOMM Incorporated
- Albert Danysh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ONLINE FUNCTIONAL TESTING FOR ERROR-CORRECTIN...
- Publication number 20190176838
- Publication date Jun 13, 2019
- Mohammad Reza KAKOEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
- Publication number 20180203698
- Publication date Jul 19, 2018
- Intel Corporation
- Maxim Loktyukhin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION-BASED SYNCHRONIZATION OF OPERATIONS INCLUDING AT LEAST...
- Publication number 20180081687
- Publication date Mar 22, 2018
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA STORAGE AT CONTIGUOUS MEMORY ADDRESSES
- Publication number 20180081803
- Publication date Mar 22, 2018
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIECEWISE POLYNOMIAL EVALUATION INSTRUCTION
- Publication number 20180081634
- Publication date Mar 22, 2018
- QUALCOMM Incorporated
- Eric Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCATTER TO GATHER OPERATION
- Publication number 20170371657
- Publication date Dec 28, 2017
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING VOLTAGE DEVIATIONS IN PROCESSING SYSTEMS
- Publication number 20170083066
- Publication date Mar 23, 2017
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS
- Publication number 20170046153
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TABLE LOOKUP USING SIMD INSTRUCTIONS
- Publication number 20170046156
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SINGLE-INSTRUCTION-MULTIPLE-DATA INSTRUCTIONS
- Publication number 20170046168
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIXED-WIDTH SIMD OPERATIONS USING EVEN/ODD REGISTER PAIRS FOR WIDE...
- Publication number 20170024209
- Publication date Jan 26, 2017
- QUALCOMM Incorporated
- Eric Wayne MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLIDING WINDOW OPERATION
- Publication number 20170024218
- Publication date Jan 26, 2017
- QUALCOMM Incorporated
- Eric MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMD INSTRUCTIONS FOR MULTI-STAGE CUBE NETWORKS
- Publication number 20170024208
- Publication date Jan 26, 2017
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTION HARDWARE FOR LOAD AND STORE OPERATION ALIGNMENT
- Publication number 20160364147
- Publication date Dec 15, 2016
- QUALCOMM Incorporated
- Eric Wayne Mahurin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, APPARATUS, AND METHOD FOR TEMPORARY LOAD INSTRUCTION
- Publication number 20160357558
- Publication date Dec 8, 2016
- QUALCOMM Incorporated
- Eric MAHURIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COPROCESSOR FOR OUT-OF-ORDER LOADS
- Publication number 20160092238
- Publication date Mar 31, 2016
- QUALCOMM Incorporated
- Lucian CODRESCU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZATION OF SCALAR OPERATIONS BY VECTOR PROCESSORS USING DAT...
- Publication number 20160026607
- Publication date Jan 28, 2016
- QUALCOMM Incorporated
- Lucian Codrescu
- G06 - COMPUTING CALCULATING COUNTING

Eric Wayne MAHURIN

Person

Patents Grantslast 30 patents

Hybrid convolution operation

Constraining function approximation hardware integrated with fixed-...

Memory access management

Inserting a proxy read instruction in an instruction pipeline in a...

Power control based on performance modification through pulse modul...

System, apparatus, and method for a transient load instruction with...

System and method of loading and replication of sub-vector values

Multi-thread power limiting via shared limit

Proactive clock gating system to mitigate supply voltage droops

Processor to perform a bit range isolation instruction

System and method for online functional testing for error-correctin...

Processor to perform a bit range isolation instruction

System-on-chip (SoC) to perform a bit range isolation instruction

Mixed-width SIMD operations using even/odd register pairs for wide...

Instruction-based synchronization of operations including at least...

Sliding window operation

SIMD instructions for multi-stage cube networks

Hand held device to perform a bit range isolation instruction

System and method of floating point multiply operation processing

Data storage at contiguous memory addresses

Controlling voltage deviations in processing systems

Coprocessor for out-of-order loads

Functional unit for vector leading zeroes, vector trailing zeroes,...

Reducing power consumption and resource utilization during miss loo...

Bit range isolation instructions, methods, and apparatus

Prefetching load data in lookahead mode and invalidating architectu...

Multiplexing using product-of-sums and sum-of-products

Integrated circuit design with cell-based macros

Circuit for parity tree structure

Instruction decode unit producing instruction operand information i...

Patents Applicationslast 30 patents

SINGLE INSTRUCTION MULTIPLE DATA (SIMD) SPARSE DECOMPRESSION WITH V...

SIMULATED LOW BIT-WIDTH QUANTIZATION USING BIT SHIFTED NEURAL NETWO...

INSERTING A PROXY READ INSTRUCTION IN AN INSTRUCTION PIPELINE IN A...

Artificial Intelligence Processor Architecture For Dynamic Scaling...

REDUCED RESULT MATRIX

MULTI-THREAD POWER LIMITING VIA SHARED LIMIT

MEMORY ACCESS MANAGEMENT

HYBRID CONVOLUTION OPERATION

POWER CONTROL BASED ON PERFORMANCE MODIFICATION THROUGH PULSE MODUL...

CONSTRAINING FUNCTION APPROXIMATION HARDWARE INTEGRATED WITH FIXED-...

PROACTIVE CLOCK GATING SYSTEM TO MITIGATE SUPPLY VOLTAGE DROOPS

SYSTEM AND METHOD OF LOADING AND REPLICATION OF SUB-VECTOR VALUES

SYSTEM AND METHOD OF FLOATING POINT MULTIPLY OPERATION PROCESSING

SYSTEM AND METHOD FOR ONLINE FUNCTIONAL TESTING FOR ERROR-CORRECTIN...

PROCESSOR TO PERFORM A BIT RANGE ISOLATION INSTRUCTION

INSTRUCTION-BASED SYNCHRONIZATION OF OPERATIONS INCLUDING AT LEAST...

DATA STORAGE AT CONTIGUOUS MEMORY ADDRESSES

PIECEWISE POLYNOMIAL EVALUATION INSTRUCTION

SCATTER TO GATHER OPERATION

CONTROLLING VOLTAGE DEVIATIONS IN PROCESSING SYSTEMS

SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS

TABLE LOOKUP USING SIMD INSTRUCTIONS

SCALABLE SINGLE-INSTRUCTION-MULTIPLE-DATA INSTRUCTIONS

MIXED-WIDTH SIMD OPERATIONS USING EVEN/ODD REGISTER PAIRS FOR WIDE...

SLIDING WINDOW OPERATION

SIMD INSTRUCTIONS FOR MULTI-STAGE CUBE NETWORKS

EXECUTION HARDWARE FOR LOAD AND STORE OPERATION ALIGNMENT

SYSTEM, APPARATUS, AND METHOD FOR TEMPORARY LOAD INSTRUCTION

COPROCESSOR FOR OUT-OF-ORDER LOADS

PARALLELIZATION OF SCALAR OPERATIONS BY VECTOR PROCESSORS USING DAT...