Erik A. Nelson

Person

Waterbury, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for margin testing integrated circuits using...
- Patent number 8,854,073
- Issue date Oct 7, 2014
- International Business Machines Corporation
- David A. Grosch
- G01 - MEASURING TESTING
Information Patent Grant
Reference level generation with offset compensation for sense ampli...
- Patent number 8,125,840
- Issue date Feb 28, 2012
- International Business Machines Corporation
- John E. Barth, Jr.
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing embedded DRAM arrays
- Patent number 7,237,165
- Issue date Jun 26, 2007
- International Business Machines Corporation
- Laura S. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing logic and embedded memory in parallel
- Patent number 7,103,814
- Issue date Sep 5, 2006
- International Business Machines Corporation
- William R. Corbin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing embedded DRAM arrays
- Patent number 7,073,100
- Issue date Jul 4, 2006
- International Business Machines Corporation
- Laura S. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for merging multiple fuse decompression serial bi...
- Patent number 6,856,569
- Issue date Feb 15, 2005
- International Business Machines Corporation
- Erik A. Nelson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for guaranteeing a minimum data strobe valid window and a mi...
- Patent number 6,708,298
- Issue date Mar 16, 2004
- International Business Machines Corporation
- William E. Corbin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing and guaranteeing that skew between two signals m...
- Patent number 6,658,604
- Issue date Dec 2, 2003
- International Business Machines Corporation
- William R. Corbin
- G11 - INFORMATION STORAGE
Information Patent Grant
Self timing interlock circuit for embedded DRAM
- Patent number 6,577,548
- Issue date Jun 10, 2003
- International Business Machines Corporation
- John E. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Duty-cycle-efficient SRAM cell test
- Patent number 6,449,200
- Issue date Sep 10, 2002
- International Business Machines Corporation
- Erik A. Nelson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT METHODS AND APPARATUS FOR MARGIN TESTING INTEGRATED CIRCUITS
- Publication number 20130069678
- Publication date Mar 21, 2013
- International Business Machines Corporation
- David Grosch
- G01 - MEASURING TESTING
Information Patent Application
REFERENCE LEVEL GENERATION WITH OFFSET COMPENSATION FOR SENSE AMPLI...
- Publication number 20110051532
- Publication date Mar 3, 2011
- International Business Machines Corporation
- John E. Barth, JR.
- G11 - INFORMATION STORAGE
Information Patent Application
Method for testing embedded DRAM arrays
- Publication number 20050088888
- Publication date Apr 28, 2005
- Laura S. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Application
Method and System For Merging Multiple Fuse Decompression Serial Bi...
- Publication number 20040136257
- Publication date Jul 15, 2004
- International Business Machines Corporation
- Erik A. Nelson
- G11 - INFORMATION STORAGE
Information Patent Application
Method for testing embedded DRAM arrays
- Publication number 20040093539
- Publication date May 13, 2004
- International Business Machines Corporation
- Laura S. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Application
Testing logic and embedded memory in parallel
- Publication number 20040083412
- Publication date Apr 29, 2004
- International Business Machines Corporation
- William R. Corbin
- G01 - MEASURING TESTING
Information Patent Application
Method for guaranteeing a minimum data strobe valid window and a mi...
- Publication number 20020099987
- Publication date Jul 25, 2002
- International Business Machines Corporation
- William R. Corbin
- G11 - INFORMATION STORAGE

Erik A. Nelson

Person

Patents Grantslast 30 patents

Methods and apparatus for margin testing integrated circuits using...

Reference level generation with offset compensation for sense ampli...

Method for testing embedded DRAM arrays

Testing logic and embedded memory in parallel

Method for testing embedded DRAM arrays

Method and system for merging multiple fuse decompression serial bi...

Method for guaranteeing a minimum data strobe valid window and a mi...

Method for testing and guaranteeing that skew between two signals m...

Self timing interlock circuit for embedded DRAM

Duty-cycle-efficient SRAM cell test

Patents Applicationslast 30 patents

EFFICIENT METHODS AND APPARATUS FOR MARGIN TESTING INTEGRATED CIRCUITS

REFERENCE LEVEL GENERATION WITH OFFSET COMPENSATION FOR SENSE AMPLI...

Method for testing embedded DRAM arrays

Method and System For Merging Multiple Fuse Decompression Serial Bi...

Method for testing embedded DRAM arrays

Testing logic and embedded memory in parallel

Method for guaranteeing a minimum data strobe valid window and a mi...