Erik Geiss

Person

Saratoga Springs, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Asymmetric overlay mark for overlay measurement
- Patent number 10,707,175
- Issue date Jul 7, 2020
- GLOBALFOUNDRIES Inc.
- Wei Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scaled memory structures or other logic devices with middle of the...
- Patent number 10,475,890
- Issue date Nov 12, 2019
- GLOBALFOUNDRIES Inc.
- Haiting Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating FinFET integrated circuits with simultaneou...
- Patent number 9,397,004
- Issue date Jul 19, 2016
- GLOBALFOUNDRIES, INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming self-aligned contacts for a semiconductor device
- Patent number 8,927,407
- Issue date Jan 6, 2015
- GLOBALFOUNDRIES Inc.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning method for fabrication of a semiconductor device
- Patent number 8,592,302
- Issue date Nov 26, 2013
- GLOBALFOUNDRIES, INC.
- Erik P. Geiss
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of semiconductor manufacturing for small features
- Patent number 8,071,485
- Issue date Dec 6, 2011
- GLOBALFOUNDRIES Inc.
- Doug H. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two step optical planarizing layer etch
- Patent number 7,601,641
- Issue date Oct 13, 2009
- Global Foundries, Inc.
- Erik Geiss
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ASYMMETRIC OVERLAY MARK FOR OVERLAY MEASUREMENT
- Publication number 20190363053
- Publication date Nov 28, 2019
- GLOBALFOUNDRIES INC.
- Wei Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCALED MEMORY STRUCTURES OR OTHER LOGIC DEVICES WITH MIDDLE OF THE...
- Publication number 20190109197
- Publication date Apr 11, 2019
- GLOBALFOUNDRIES INC.
- Haiting WANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOU...
- Publication number 20150214113
- Publication date Jul 30, 2015
- GLOBALFOUNDRIES, Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Self-Aligned Contacts for a Semiconductor Device
- Publication number 20130189833
- Publication date Jul 25, 2013
- GLOBALFOUNDRIES INC.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNING METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE
- Publication number 20130137269
- Publication date May 30, 2013
- GLOBALFOUNDRIES INC.
- Erik P. Geiss
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF SEMICONDUCTOR MANUFACTURING FOR SMALL FEATURES
- Publication number 20100327412
- Publication date Dec 30, 2010
- GLOBALFOUNDRIES INC.
- Doug H. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO STEP OPTICAL PLANARIZING LAYER ETCH
- Publication number 20090246959
- Publication date Oct 1, 2009
- Advanced Micro Devices, Inc.
- Erik GEISS
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Asymmetric overlay mark for overlay measurement

Scaled memory structures or other logic devices with middle of the...

Methods for fabricating FinFET integrated circuits with simultaneou...

Method of forming self-aligned contacts for a semiconductor device

Patterning method for fabrication of a semiconductor device

Method of semiconductor manufacturing for small features

Two step optical planarizing layer etch

Patents Applicationslast 30 patents

ASYMMETRIC OVERLAY MARK FOR OVERLAY MEASUREMENT

SCALED MEMORY STRUCTURES OR OTHER LOGIC DEVICES WITH MIDDLE OF THE...

METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOU...

Method of Forming Self-Aligned Contacts for a Semiconductor Device

PATTERNING METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE

METHOD OF SEMICONDUCTOR MANUFACTURING FOR SMALL FEATURES

TWO STEP OPTICAL PLANARIZING LAYER ETCH