Erik Jan Marinissen

Person

Leuven, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Two-step interconnect testing of semiconductor dies
- Patent number 9,678,142
- Issue date Jun 13, 2017
- IMEC
- Julien Ryckaert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transition delay detector for interconnect test
- Patent number 9,568,536
- Issue date Feb 14, 2017
- IMEC
- Sandeep Kumar Goel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test access architecture for TSV-based 3D stacked ICS
- Patent number 9,239,359
- Issue date Jan 19, 2016
- IMEC
- Erik Jan Marinissen
- G01 - MEASURING TESTING
Information Patent Grant
Testing of an integrated circuit that contains secret information
- Patent number 9,041,411
- Issue date May 26, 2015
- NXP B.V.
- Erik J. Marinissen
- G01 - MEASURING TESTING
Information Patent Grant
Controlled toggle rate of non-test signals during modular scan test...
- Patent number 8,914,689
- Issue date Dec 16, 2014
- Cadence Design Systems, Inc.
- Erik Jan Marinissen
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit for testing through-silicon-vias in 3D integrated circ...
- Patent number 8,773,157
- Issue date Jul 8, 2014
- IMEC
- Mustafa Badaroglu
- G01 - MEASURING TESTING
Information Patent Grant
On-chip testing using time-to-digital conversion
- Patent number 8,680,874
- Issue date Mar 25, 2014
- IMEC
- Nikolaos Minas
- G01 - MEASURING TESTING
Information Patent Grant
Method and device for testing TSVS in a 3D chip stack
- Patent number 8,593,170
- Issue date Nov 26, 2013
- IMEC
- Geert Van der Plas
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TWO-STEP INTERCONNECT TESTING OF SEMICONDUCTOR DIES
- Publication number 20140300379
- Publication date Oct 9, 2014
- IMEC
- Julien RYCKAERT
- G01 - MEASURING TESTING
Information Patent Application
TRANSITION DELAY DETECTOR FOR INTERCONNECT TEST
- Publication number 20140111243
- Publication date Apr 24, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Application
CONTROLLED TOGGLE RATE OF NON-TEST SIGNALS DURING MODULAR SCAN TEST...
- Publication number 20140082421
- Publication date Mar 20, 2014
- Cadence Design Systems, Inc.
- Erik Jan Marinissen
- G01 - MEASURING TESTING
Information Patent Application
TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS
- Publication number 20130024737
- Publication date Jan 24, 2013
- Stichting IMEC Nederland
- Erik Jan Marinissen
- G01 - MEASURING TESTING
Information Patent Application
FAULT MODE CIRCUITS
- Publication number 20130002272
- Publication date Jan 3, 2013
- IMEC
- Mustafa Badaroglu
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP TESTING USING TIME-TO-DIGITAL CONVERSION
- Publication number 20120025846
- Publication date Feb 2, 2012
- IMEC
- Nikolaos Minas
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND DEVICE FOR TESTING TSVS IN A 3D CHIP STACK
- Publication number 20110102011
- Publication date May 5, 2011
- IMEC
- Geert Van der Plas
- G01 - MEASURING TESTING

Erik Jan Marinissen

Person

Patents Grantslast 30 patents

Two-step interconnect testing of semiconductor dies

Transition delay detector for interconnect test

Test access architecture for TSV-based 3D stacked ICS

Testing of an integrated circuit that contains secret information

Controlled toggle rate of non-test signals during modular scan test...

Test circuit for testing through-silicon-vias in 3D integrated circ...

On-chip testing using time-to-digital conversion

Method and device for testing TSVS in a 3D chip stack

Patents Applicationslast 30 patents

TWO-STEP INTERCONNECT TESTING OF SEMICONDUCTOR DIES

TRANSITION DELAY DETECTOR FOR INTERCONNECT TEST

CONTROLLED TOGGLE RATE OF NON-TEST SIGNALS DURING MODULAR SCAN TEST...

TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS

FAULT MODE CIRCUITS

ON-CHIP TESTING USING TIME-TO-DIGITAL CONVERSION

METHOD AND DEVICE FOR TESTING TSVS IN A 3D CHIP STACK