Ernst Mayer

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Cupertino, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Tiered schematic-driven layout synchronization in electronic design...
- Patent number 8,762,912
- Issue date Jun 24, 2014
- Synopsys, Inc.
- Wern-Jieh Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reverse routing methods for integrated circuits having a hierarchic...
- Patent number 7,725,863
- Issue date May 25, 2010
- Agate Logic, Inc.
- Ernst Mayer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN...
- Publication number 20110107281
- Publication date May 5, 2011
- Synopsys, Inc.
- Wern-Jieh Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reverse routing methods for integrated circuits having a hierarchic...
- Publication number 20080209383
- Publication date Aug 28, 2008
- Agate Logic, Inc.
- Ernst Mayer
- G06 - COMPUTING CALCULATING COUNTING