Ertugrul Demircan

Person

Eugene, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for verifying design rule checks
- Patent number 9,934,349
- Issue date Apr 3, 2018
- NXP USA, INC.
- Inder Mohan Bhawnani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design using pre-marked circuit element object l...
- Patent number 9,652,577
- Issue date May 16, 2017
- NXP USA, INC.
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for electromigration stress mitigation in interconnects...
- Patent number 9,245,086
- Issue date Jan 26, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inductive element with interrupter region and method for forming
- Patent number 9,219,107
- Issue date Dec 22, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Prioritized design for manufacturing virtualization with design rul...
- Patent number 9,026,970
- Issue date May 5, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Kenneth J. Danti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for electromigration stress determination in interconnec...
- Patent number 8,793,632
- Issue date Jul 29, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inductive element with interrupter region
- Patent number 8,766,402
- Issue date Jul 1, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for physical verification using network segment c...
- Patent number 8,713,498
- Issue date Apr 29, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for electromigration stress determination in interconnec...
- Patent number 8,510,695
- Issue date Aug 13, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits with edge-adjacent devices having reactance values
- Patent number 8,431,970
- Issue date Apr 30, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with capacitor and/or inductor and method of m...
- Patent number 7,820,520
- Issue date Oct 26, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Primitive cell method for front end physical design
- Patent number 7,386,821
- Issue date Jun 10, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Jack M. Higman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated vertical stack capacitor
- Patent number 6,765,778
- Issue date Jul 20, 2004
- FREESCALE SEMICONDUCTOR, INC.
- Yang Du
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR VERIFYING DESIGN RULE CHECKS
- Publication number 20160283642
- Publication date Sep 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- INDER MOHAN BHAWNANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Design Using Pre-Marked Circuit Element Object L...
- Publication number 20160098510
- Publication date Apr 7, 2016
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS
- Publication number 20150178438
- Publication date Jun 25, 2015
- ERTUGRUL DEMIRCAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR ELECTROMIGRATION STRESS MITIGATION IN INTERCONNECTS...
- Publication number 20150046893
- Publication date Feb 12, 2015
- FREESCALE SEMICONDUCTOR, INC.
- ERTUGRUL DEMIRCAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING
- Publication number 20140273391
- Publication date Sep 18, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Prioritized Design for Manufacturing Virtualization with Design Rul...
- Publication number 20140258951
- Publication date Sep 11, 2014
- Kenneth J. Danti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Electromigration Stress Determination in Interconnec...
- Publication number 20130326448
- Publication date Dec 5, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING
- Publication number 20130320490
- Publication date Dec 5, 2013
- Ertugrul Demircan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM FOR PHYSICAL VERIFICATION USING NETWORK SEGMENT C...
- Publication number 20130055184
- Publication date Feb 28, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF M...
- Publication number 20110001214
- Publication date Jan 6, 2011
- FREESCALE SEMICONDUCTOR, INC.
- ERTUGRUL DEMIRCAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF M...
- Publication number 20080230873
- Publication date Sep 25, 2008
- Ertugrul Demircan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRIMITIVE CELL METHOD FOR FRONT END PHYSICAL DESIGN
- Publication number 20080005717
- Publication date Jan 3, 2008
- Jack M. Higman
- G06 - COMPUTING CALCULATING COUNTING

Ertugrul Demircan

Person

Patents Grantslast 30 patents

Method for verifying design rule checks

Integrated circuit design using pre-marked circuit element object l...

Techniques for electromigration stress mitigation in interconnects...

Inductive element with interrupter region and method for forming

Prioritized design for manufacturing virtualization with design rul...

Techniques for electromigration stress determination in interconnec...

Inductive element with interrupter region

Method and system for physical verification using network segment c...

Techniques for electromigration stress determination in interconnec...

Integrated circuits with edge-adjacent devices having reactance values

Semiconductor device with capacitor and/or inductor and method of m...

Primitive cell method for front end physical design

Integrated vertical stack capacitor

Patents Applicationslast 30 patents

METHOD FOR VERIFYING DESIGN RULE CHECKS

Integrated Circuit Design Using Pre-Marked Circuit Element Object L...

SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS

TECHNIQUES FOR ELECTROMIGRATION STRESS MITIGATION IN INTERCONNECTS...

INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING

Prioritized Design for Manufacturing Virtualization with Design Rul...

Techniques for Electromigration Stress Determination in Interconnec...

INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING

METHOD AND SYSTEM FOR PHYSICAL VERIFICATION USING NETWORK SEGMENT C...

SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF M...

SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF M...

PRIMITIVE CELL METHOD FOR FRONT END PHYSICAL DESIGN