Erwin Yu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory array structures and methods of forming memory array structures
- Patent number 12,183,396
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Dan Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Microelectronic devices, and related memory devices and electronic...
- Patent number 12,171,096
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Erwin E. Yu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Microelectronic devices, and related memory devices and electronic...
- Patent number 12,101,932
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Erwin E. Yu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Managing sub-block erase operations in a memory sub-system
- Patent number 12,068,037
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kalyan Chakravarthy Kavalipurapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective management of erase operations in memory devices that ena...
- Patent number 11,942,159
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Chulbum Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices with four data line bias levels
- Patent number 11,915,758
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing programming convergence associated with memory cells of a...
- Patent number 11,862,257
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Jun Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing sub-block erase operations in a memory sub-system
- Patent number 11,749,353
- Issue date Sep 5, 2023
- Micron Technology, Inc.
- Kalyan Chakravarthy Kavalipurapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices with four data line bias levels
- Patent number 11,562,791
- Issue date Jan 24, 2023
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense circuit to sense two states of a memory cell
- Patent number 11,557,351
- Issue date Jan 17, 2023
- Micron Technology, Inc.
- Luyen Tien Vu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array structures and methods for determination of resistive...
- Patent number 11,557,341
- Issue date Jan 17, 2023
- Micron Technology, Inc.
- Dan Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing programming convergence associated with memory cells of a...
- Patent number 11,532,367
- Issue date Dec 20, 2022
- Micron Technology, Inc.
- Jun Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for determination of capacitive and resistive...
- Patent number 11,442,091
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Dan Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing sub-block erase operations in a memory sub-system
- Patent number 11,335,412
- Issue date May 17, 2022
- Micron Technology, Inc.
- Kalyan Chakravarthy Kavalipurapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature compensation in memory sensing
- Patent number 10,790,029
- Issue date Sep 29, 2020
- Micron Technology, Inc.
- Luyen Vu
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense matching for hard and soft memory reads
- Patent number 10,163,500
- Issue date Dec 25, 2018
- Intel Corporation
- Erwin E. Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature compensation in memory sensing
- Patent number 10,127,988
- Issue date Nov 13, 2018
- Micron Technology, Inc.
- Luyen Vu
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing verification checks when programming a memory device
- Patent number 10,049,759
- Issue date Aug 14, 2018
- Intel Corporation
- Kalyan Kavalipurapu
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing verification checks when programming a memory device
- Patent number 9,842,655
- Issue date Dec 12, 2017
- Intel Corporation
- Kalyan Kavalipurapu
- G11 - INFORMATION STORAGE
Information Patent Grant
On demand knockout of coarse sensing based on dynamic source bounce...
- Patent number 9,633,744
- Issue date Apr 25, 2017
- Intel Corporation
- Kalyan C. Kavalipurapu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for programming flash memory
- Patent number 8,179,726
- Issue date May 15, 2012
- Micron Technology, Inc.
- Erwin E. Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for programming flash memory
- Patent number 7,974,129
- Issue date Jul 5, 2011
- Micron Technologies, Inc.
- Erwin E. Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for programming flash memory
- Patent number 7,663,925
- Issue date Feb 16, 2010
- Micron Technology Inc.
- Erwin E. Yu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICES INCLUDING PAD STRUCTURES
- Publication number 20250098159
- Publication date Mar 20, 2025
- Micron Technology, Inc.
- Erwin E. Yu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMORY DEVICES AND ELECTRONIC SYSTEMS
- Publication number 20250008727
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Erwin E. Yu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SEEDING BIAS CONTROL FOR SUB-BLOCK GROUPS IN A MEMORY DEVICE
- Publication number 20240428862
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENA...
- Publication number 20240203508
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Chulbum Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING SENSE AMPLIFIER LATCH AND DATA LATCH VOLTAGE TO REDUCE STA...
- Publication number 20240170075
- Publication date May 23, 2024
- Micron Technology, Inc.
- Kwang Ho Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
- Publication number 20230360709
- Publication date Nov 9, 2023
- Micron Technology, Inc.
- Kalyan Chakravarthy Kavalipurapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY STRUCTURES AND METHODS OF FORMING MEMORY ARRAY STRUCTURES
- Publication number 20230170016
- Publication date Jun 1, 2023
- Micron Technology, Inc.
- Dan Xu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
- Publication number 20230162793
- Publication date May 25, 2023
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A...
- Publication number 20230078401
- Publication date Mar 16, 2023
- Micron Technology, Inc.
- Jun Xu
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENA...
- Publication number 20230063656
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Chulbum Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC...
- Publication number 20230066649
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Erwin E. Yu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC...
- Publication number 20230047662
- Publication date Feb 16, 2023
- Micron Technology, Inc.
- Erwin E. Yu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
- Publication number 20230039026
- Publication date Feb 9, 2023
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS FOR DETERMINATION OF CAPACITIVE AND RESISTIVE CHARACTERIS...
- Publication number 20220404408
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Dan Xu
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
- Publication number 20220277795
- Publication date Sep 1, 2022
- Micron Technology, Inc.
- Kalyan Chakravarthy Kavalipurapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENSE CIRCUIT TO SENSE TWO STATES OF A MEMORY CELL
- Publication number 20220208278
- Publication date Jun 30, 2022
- Micron Technology, Inc.
- Luyen Tien Vu
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A...
- Publication number 20220180952
- Publication date Jun 9, 2022
- Micron Technology, Inc.
- Jun Xu
- G11 - INFORMATION STORAGE
Information Patent Application
APPRATUS AND METHODS FOR DETERMINATION OF CAPACITIVE AND RESISTIVE...
- Publication number 20210199703
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Dan Xu
- G01 - MEASURING TESTING
Information Patent Application
MEMORY ARRAY STRUCTURES AND METHODS FOR DETERMINATION OF RESISTIVE...
- Publication number 20210201993
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Dan Xu
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
- Publication number 20210202009
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Kalyan Chakravarthy Kavalipurapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEMPERATURE COMPENSATION IN MEMORY SENSING
- Publication number 20180366203
- Publication date Dec 20, 2018
- Micron Technology, Inc.
- Luyen Vu
- G11 - INFORMATION STORAGE
Information Patent Application
TEMPERATURE COMPENSATION IN MEMORY SENSING
- Publication number 20180061497
- Publication date Mar 1, 2018
- Micron Technology, Inc.
- Luyen Vu
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING VERIFICATION CHECKS WHEN PROGRAMMING A MEMORY DEVICE
- Publication number 20170169896
- Publication date Jun 15, 2017
- Intel Corporation
- Kalyan Kavalipurapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING VERIFICATION CHECKS WHEN PROGRAMMING A MEMORY DEVICE
- Publication number 20170162272
- Publication date Jun 8, 2017
- Intel Corporation
- Kalyan Kavalipurapu
- G11 - INFORMATION STORAGE
Information Patent Application
ON DEMAND KNOCKOUT OF COARSE SENSING BASED ON DYNAMIC SOURCE BOUNCE...
- Publication number 20170084347
- Publication date Mar 23, 2017
- Intel Corporation
- Kalyan C. Kavalipurapu
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY
- Publication number 20110235429
- Publication date Sep 29, 2011
- Erwin E. Yu
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY
- Publication number 20100110797
- Publication date May 6, 2010
- Erwin E. Yu
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for programming flash memory
- Publication number 20070263449
- Publication date Nov 15, 2007
- Micron Technology, Inc.
- Erwin E. Yu
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Memory array structures and methods of forming memory array structures

Microelectronic devices, and related memory devices and electronic...

Microelectronic devices, and related memory devices and electronic...

Managing sub-block erase operations in a memory sub-system

Selective management of erase operations in memory devices that ena...

Memory devices with four data line bias levels

Managing programming convergence associated with memory cells of a...

Managing sub-block erase operations in a memory sub-system

Memory devices with four data line bias levels

Sense circuit to sense two states of a memory cell

Memory array structures and methods for determination of resistive...

Managing programming convergence associated with memory cells of a...

Apparatus and methods for determination of capacitive and resistive...

Managing sub-block erase operations in a memory sub-system

Temperature compensation in memory sensing

Sense matching for hard and soft memory reads

Temperature compensation in memory sensing

Reducing verification checks when programming a memory device

Reducing verification checks when programming a memory device

On demand knockout of coarse sensing based on dynamic source bounce...

Method and apparatus for programming flash memory

Method and apparatus for programming flash memory

Method and apparatus for programming flash memory

Patents Applicationslast 30 patents

MEMORY DEVICES INCLUDING PAD STRUCTURES

MEMORY DEVICES AND ELECTRONIC SYSTEMS

SEEDING BIAS CONTROL FOR SUB-BLOCK GROUPS IN A MEMORY DEVICE

SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENA...

MANAGING SENSE AMPLIFIER LATCH AND DATA LATCH VOLTAGE TO REDUCE STA...

MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM

MEMORY ARRAY STRUCTURES AND METHODS OF FORMING MEMORY ARRAY STRUCTURES

MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS

MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A...

SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENA...

MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC...

MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC...

MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS

APPARATUS FOR DETERMINATION OF CAPACITIVE AND RESISTIVE CHARACTERIS...

MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM

SENSE CIRCUIT TO SENSE TWO STATES OF A MEMORY CELL

MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A...

APPRATUS AND METHODS FOR DETERMINATION OF CAPACITIVE AND RESISTIVE...

MEMORY ARRAY STRUCTURES AND METHODS FOR DETERMINATION OF RESISTIVE...

MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM

TEMPERATURE COMPENSATION IN MEMORY SENSING

TEMPERATURE COMPENSATION IN MEMORY SENSING

REDUCING VERIFICATION CHECKS WHEN PROGRAMMING A MEMORY DEVICE

REDUCING VERIFICATION CHECKS WHEN PROGRAMMING A MEMORY DEVICE

ON DEMAND KNOCKOUT OF COARSE SENSING BASED ON DYNAMIC SOURCE BOUNCE...

METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY

METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY

Method and apparatus for programming flash memory