Eskinder Hailu

Person

Cary, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low-power, low-latency time-to-digital-converter-based serial link
- Patent number 10,965,442
- Issue date Mar 30, 2021
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fixing dead-zone in clock data recovery circuits
- Patent number 10,637,637
- Issue date Apr 28, 2020
- QUALCOMM Incorporated
- Hadi Goudarzi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Quadrature clock generation with injection locking
- Patent number 10,476,434
- Issue date Nov 12, 2019
- QUALCOMM Incorporated
- Bupesh Pandita
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Serializer-deserializer with frequency doubler
- Patent number 10,419,204
- Issue date Sep 17, 2019
- QUALCOMM Incorporated
- Eskinder Hailu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SerDes with adaptive clock data recovery
- Patent number 10,389,366
- Issue date Aug 20, 2019
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimizing clock/data recovery power while maintaining link stabili...
- Patent number 10,382,190
- Issue date Aug 13, 2019
- QUALCOMM Incorporated
- Rajeev Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for frequency calibration of voltage controlle...
- Patent number 10,355,701
- Issue date Jul 16, 2019
- QUALCOMM Incorporated
- Bupesh Pandita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid phase-locked loop
- Patent number 10,355,702
- Issue date Jul 16, 2019
- QUALCOMM Incorporated
- Zhuo Gao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay locked loop (DLL) employing pulse to digital converter (PDC)...
- Patent number 9,998,126
- Issue date Jun 12, 2018
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse to digital converter
- Patent number 9,971,312
- Issue date May 15, 2018
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compact phase interpolator
- Patent number 9,755,817
- Issue date Sep 5, 2017
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for combining currents from passive equalizer...
- Patent number 9,602,317
- Issue date Mar 21, 2017
- QUALCOMM Incorporated
- Eskinder Hailu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fractional phase locked loop (PLL) architecture
- Patent number 9,577,646
- Issue date Feb 21, 2017
- QUALCOMM Incorporated
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ENCODING DIFFERENTIAL SIGNALS FOR POWER AND NOISE REDUCTION
- Publication number 20240329715
- Publication date Oct 3, 2024
- Intel Corporation
- Amit K. Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER, LOW-LATENCY TIME-TO-DIGITAL-CONVERTER-BASED SERIAL LINK
- Publication number 20200106597
- Publication date Apr 2, 2020
- QUALCOMM Incorporated
- Eskinder Hailu
- G04 - HOROLOGY
Information Patent Application
FIXING DEAD-ZONE IN CLOCK DATA RECOVERY CIRCUITS
- Publication number 20200099506
- Publication date Mar 26, 2020
- QUALCOMM Incorporated
- Hadi GOUDARZI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
QUADRATURE CLOCK GENERATION WITH INJECTION LOCKING
- Publication number 20190363674
- Publication date Nov 28, 2019
- QUALCOMM Incorporated
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHOD FOR FREQUENCY CALIBRATION OF VOLTAGE CONTROLLE...
- Publication number 20190052278
- Publication date Feb 14, 2019
- QUALCOMM Incorporated
- Bupesh Pandita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID PHASE-LOCKED LOOP
- Publication number 20190028108
- Publication date Jan 24, 2019
- QUALCOMM Incorporated
- Zhuo Gao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SERIALIZER-DESERIALIZER WITH FREQUENCY DOUBLER
- Publication number 20190013929
- Publication date Jan 10, 2019
- QUALCOMM Incorporated
- Eskinder Hailu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SERDES WITH ADAPTIVE CLOCK DATA RECOVERY
- Publication number 20190007053
- Publication date Jan 3, 2019
- QUALCOMM Incorporated
- Eskinder Hailu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMPACT PHASE INTERPOLATOR
- Publication number 20170222789
- Publication date Aug 3, 2017
- QUALCOMM Incorporated
- Eskinder Hailu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER...
- Publication number 20170104616
- Publication date Apr 13, 2017
- QUALCOMM Incorporated
- Eskinder Hailu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE
- Publication number 20170041005
- Publication date Feb 9, 2017
- QUALCOMM Incorporated
- Bupesh Pandita
- H03 - BASIC ELECTRONIC CIRCUITRY

Eskinder Hailu

Person

Patents Grantslast 30 patents

Low-power, low-latency time-to-digital-converter-based serial link

Fixing dead-zone in clock data recovery circuits

Quadrature clock generation with injection locking

Serializer-deserializer with frequency doubler

SerDes with adaptive clock data recovery

Optimizing clock/data recovery power while maintaining link stabili...

Apparatus and method for frequency calibration of voltage controlle...

Hybrid phase-locked loop

Delay locked loop (DLL) employing pulse to digital converter (PDC)...

Pulse to digital converter

Compact phase interpolator

Apparatus and method for combining currents from passive equalizer...

Fractional phase locked loop (PLL) architecture

Patents Applicationslast 30 patents

ENCODING DIFFERENTIAL SIGNALS FOR POWER AND NOISE REDUCTION

LOW-POWER, LOW-LATENCY TIME-TO-DIGITAL-CONVERTER-BASED SERIAL LINK

FIXING DEAD-ZONE IN CLOCK DATA RECOVERY CIRCUITS

QUADRATURE CLOCK GENERATION WITH INJECTION LOCKING

APPARATUS AND METHOD FOR FREQUENCY CALIBRATION OF VOLTAGE CONTROLLE...

HYBRID PHASE-LOCKED LOOP

SERIALIZER-DESERIALIZER WITH FREQUENCY DOUBLER

SERDES WITH ADAPTIVE CLOCK DATA RECOVERY

COMPACT PHASE INTERPOLATOR

APPARATUS AND METHOD FOR COMBINING CURRENTS FROM PASSIVE EQUALIZER...

NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE