Eugene James Nosowicz

Person

Vestal, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Set/reset latch with minimum single event upset
- Patent number 7,486,123
- Issue date Feb 3, 2009
- International Business Machines Corporation
- David Jia Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Set/reset latch with minimum single event upset
- Patent number 7,425,855
- Issue date Sep 16, 2008
- International Business Machines Corporation
- David Jia Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing fault tolerant phase locked l...
- Patent number 7,259,602
- Issue date Aug 21, 2007
- International Business Machines Corporation
- Eugene James Nosowicz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and latch circuit for implementing enhanced performance with...
- Patent number 7,103,857
- Issue date Sep 5, 2006
- International Business Machines Corporation
- Eugene James Nosowicz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power data storage element with enhanced noise margin
- Patent number 6,954,086
- Issue date Oct 11, 2005
- International Business Machines Corporation
- David Jia Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse generator with controlled output characteristics
- Patent number 6,661,121
- Issue date Dec 9, 2003
- International Business Machines Corporation
- Roger P. Gregor
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascode polarity hold latch having integrated set/reset capability
- Patent number 4,274,017
- Issue date Jun 16, 1981
- International Business Machines Corporation
- Eric L. Carter
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data bit assembler
- Patent number 4,153,950
- Issue date May 8, 1979
- International Business Machines Corp.
- Eugene J. Nosowicz
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SET/RESET LATCH WITH MINIMUM SINGLE EVENT UPSET
- Publication number 20080111606
- Publication date May 15, 2008
- International Business Machines Corporation
- David Jia Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for implementing fault tolerant phase locked l...
- Publication number 20070018698
- Publication date Jan 25, 2007
- International Business Machines Corporation
- Eugene James Nosowicz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Set/reset latch with minimum single event upset
- Publication number 20070013426
- Publication date Jan 18, 2007
- International Business Machines Corporation
- David Jia Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and latch circuit for implementing enhanced performance with...
- Publication number 20050149766
- Publication date Jul 7, 2005
- International Business Machines Corporation
- Eugene James Nosowicz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power data storage element with enhanced noise margin
- Publication number 20050075814
- Publication date Apr 7, 2005
- International Business Machines Corporation
- David Jia Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Electronic delay element
- Publication number 20050062511
- Publication date Mar 24, 2005
- International Business Machines Corporation
- David Jia Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Pulse generator with controlled output characteristics
- Publication number 20030052546
- Publication date Mar 20, 2003
- International Business Machines Corporation
- Roger P. Gregor
- H03 - BASIC ELECTRONIC CIRCUITRY

Eugene James Nosowicz

Person

Patents Grantslast 30 patents

Set/reset latch with minimum single event upset

Set/reset latch with minimum single event upset

Method and apparatus for implementing fault tolerant phase locked l...

Method and latch circuit for implementing enhanced performance with...

Low power data storage element with enhanced noise margin

Pulse generator with controlled output characteristics

Cascode polarity hold latch having integrated set/reset capability

Data bit assembler

Patents Applicationslast 30 patents

SET/RESET LATCH WITH MINIMUM SINGLE EVENT UPSET

Method and apparatus for implementing fault tolerant phase locked l...

Set/reset latch with minimum single event upset

Method and latch circuit for implementing enhanced performance with...

Low power data storage element with enhanced noise margin

Electronic delay element

Pulse generator with controlled output characteristics