Eyal Odiz

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Los Altos Hills, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Concurrent formal verification of logic synthesis
- Patent number 10,643,012
- Issue date May 5, 2020
- Synopsys, Inc.
- Lisa R. McIlwain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design-for-testability (DFT) insertion at register-transfer-level (...
- Patent number 10,372,858
- Issue date Aug 6, 2019
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing an integrated circuit (IC) design comprising at least on...
- Patent number 10,354,032
- Issue date Jul 16, 2019
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying and using slices in an integrated circuit (IC) design
- Patent number 9,697,314
- Issue date Jul 4, 2017
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating and using a wide-bus data structure to represent a wide-bu...
- Patent number 9,690,890
- Issue date Jun 27, 2017
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating and using a wide-gate data structure to represent a wide-g...
- Patent number 9,652,573
- Issue date May 16, 2017
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DESIGN-FOR-TESTABILITY (DFT) INSERTION AT REGISTER-TRANSFER-LEVEL (...
- Publication number 20180246996
- Publication date Aug 30, 2018
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING AN INTEGRATED CIRCUIT (IC) DESIGN COMPRISING AT LEAST ON...
- Publication number 20180107777
- Publication date Apr 19, 2018
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING